0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock & Reset Controller Binding for SC7280
0008
0009 maintainers:
0010 - Taniya Das <tdas@codeaurora.org>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks, resets and
0014 power domains on SC7280.
0015
0016 See also dt-bindings/clock/qcom,dispcc-sc7280.h.
0017
0018 properties:
0019 compatible:
0020 const: qcom,sc7280-dispcc
0021
0022 clocks:
0023 items:
0024 - description: Board XO source
0025 - description: GPLL0 source from GCC
0026 - description: Byte clock from DSI PHY
0027 - description: Pixel clock from DSI PHY
0028 - description: Link clock from DP PHY
0029 - description: VCO DIV clock from DP PHY
0030 - description: Link clock from EDP PHY
0031 - description: VCO DIV clock from EDP PHY
0032
0033 clock-names:
0034 items:
0035 - const: bi_tcxo
0036 - const: gcc_disp_gpll0_clk
0037 - const: dsi0_phy_pll_out_byteclk
0038 - const: dsi0_phy_pll_out_dsiclk
0039 - const: dp_phy_pll_link_clk
0040 - const: dp_phy_pll_vco_div_clk
0041 - const: edp_phy_pll_link_clk
0042 - const: edp_phy_pll_vco_div_clk
0043
0044 '#clock-cells':
0045 const: 1
0046
0047 '#reset-cells':
0048 const: 1
0049
0050 '#power-domain-cells':
0051 const: 1
0052
0053 reg:
0054 maxItems: 1
0055
0056 required:
0057 - compatible
0058 - reg
0059 - clocks
0060 - clock-names
0061 - '#clock-cells'
0062 - '#reset-cells'
0063 - '#power-domain-cells'
0064
0065 additionalProperties: false
0066
0067 examples:
0068 - |
0069 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
0070 #include <dt-bindings/clock/qcom,rpmh.h>
0071 clock-controller@af00000 {
0072 compatible = "qcom,sc7280-dispcc";
0073 reg = <0x0af00000 0x200000>;
0074 clocks = <&rpmhcc RPMH_CXO_CLK>,
0075 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
0076 <&dsi_phy 0>,
0077 <&dsi_phy 1>,
0078 <&dp_phy 0>,
0079 <&dp_phy 1>,
0080 <&edp_phy 0>,
0081 <&edp_phy 1>;
0082 clock-names = "bi_tcxo",
0083 "gcc_disp_gpll0_clk",
0084 "dsi0_phy_pll_out_byteclk",
0085 "dsi0_phy_pll_out_dsiclk",
0086 "dp_phy_pll_link_clk",
0087 "dp_phy_pll_vco_div_clk",
0088 "edp_phy_pll_link_clk",
0089 "edp_phy_pll_vco_div_clk";
0090 #clock-cells = <1>;
0091 #reset-cells = <1>;
0092 #power-domain-cells = <1>;
0093 };
0094 ...
