0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
0008
0009 maintainers:
0010 - Loic Poulain <loic.poulain@linaro.org>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks, resets and
0014 power domains on qcm2290.
0015
0016 See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
0017
0018 properties:
0019 compatible:
0020 const: qcom,qcm2290-dispcc
0021
0022 clocks:
0023 items:
0024 - description: Board XO source
0025 - description: Board active-only XO source
0026 - description: GPLL0 source from GCC
0027 - description: GPLL0 div source from GCC
0028 - description: Byte clock from DSI PHY
0029 - description: Pixel clock from DSI PHY
0030
0031 clock-names:
0032 items:
0033 - const: bi_tcxo
0034 - const: bi_tcxo_ao
0035 - const: gcc_disp_gpll0_clk_src
0036 - const: gcc_disp_gpll0_div_clk_src
0037 - const: dsi0_phy_pll_out_byteclk
0038 - const: dsi0_phy_pll_out_dsiclk
0039
0040 '#clock-cells':
0041 const: 1
0042
0043 '#reset-cells':
0044 const: 1
0045
0046 '#power-domain-cells':
0047 const: 1
0048
0049 reg:
0050 maxItems: 1
0051
0052 required:
0053 - compatible
0054 - reg
0055 - clocks
0056 - clock-names
0057 - '#clock-cells'
0058 - '#reset-cells'
0059 - '#power-domain-cells'
0060
0061 additionalProperties: false
0062
0063 examples:
0064 - |
0065 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
0066 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
0067 #include <dt-bindings/clock/qcom,rpmcc.h>
0068 clock-controller@5f00000 {
0069 compatible = "qcom,qcm2290-dispcc";
0070 reg = <0x5f00000 0x20000>;
0071 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
0072 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
0073 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
0074 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
0075 <&dsi0_phy 0>,
0076 <&dsi0_phy 1>;
0077 clock-names = "bi_tcxo",
0078 "bi_tcxo_ao",
0079 "gcc_disp_gpll0_clk_src",
0080 "gcc_disp_gpll0_div_clk_src",
0081 "dsi0_phy_pll_out_byteclk",
0082 "dsi0_phy_pll_out_dsiclk";
0083 #clock-cells = <1>;
0084 #reset-cells = <1>;
0085 #power-domain-cells = <1>;
0086 };
0087 ...
