0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
0008
0009 maintainers:
0010 - Taniya Das <tdas@codeaurora.org>
0011
0012 description: |
0013 Qualcomm graphics clock control module which supports the clocks, resets and
0014 power domains on MSM8998.
0015
0016 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
0017
0018 properties:
0019 compatible:
0020 const: qcom,msm8998-gpucc
0021
0022 clocks:
0023 items:
0024 - description: Board XO source
0025 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
0026
0027 clock-names:
0028 items:
0029 - const: xo
0030 - const: gpll0
0031
0032 '#clock-cells':
0033 const: 1
0034
0035 '#reset-cells':
0036 const: 1
0037
0038 '#power-domain-cells':
0039 const: 1
0040
0041 reg:
0042 maxItems: 1
0043
0044 required:
0045 - compatible
0046 - reg
0047 - clocks
0048 - clock-names
0049 - '#clock-cells'
0050 - '#reset-cells'
0051 - '#power-domain-cells'
0052
0053 additionalProperties: false
0054
0055 examples:
0056 - |
0057 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
0058 #include <dt-bindings/clock/qcom,rpmcc.h>
0059 clock-controller@5065000 {
0060 compatible = "qcom,msm8998-gpucc";
0061 #clock-cells = <1>;
0062 #reset-cells = <1>;
0063 #power-domain-cells = <1>;
0064 reg = <0x05065000 0x9000>;
0065 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>;
0066 clock-names = "xo", "gpll0";
0067 };
0068 ...
