0001 High-Frequency PLL (HFPLL)
0002
0003 PROPERTIES
0004
0005 - compatible:
0006 Usage: required
0007 Value type: <string>:
0008 shall contain only one of the following. The generic
0009 compatible "qcom,hfpll" should be also included.
0010
0011 "qcom,hfpll-ipq8064", "qcom,hfpll"
0012 "qcom,hfpll-apq8064", "qcom,hfpll"
0013 "qcom,hfpll-msm8974", "qcom,hfpll"
0014 "qcom,hfpll-msm8960", "qcom,hfpll"
0015
0016 - reg:
0017 Usage: required
0018 Value type: <prop-encoded-array>
0019 Definition: address and size of HPLL registers. An optional second
0020 element specifies the address and size of the alias
0021 register region.
0022
0023 - clocks:
0024 Usage: required
0025 Value type: <prop-encoded-array>
0026 Definition: reference to the xo clock.
0027
0028 - clock-names:
0029 Usage: required
0030 Value type: <stringlist>
0031 Definition: must be "xo".
0032
0033 - clock-output-names:
0034 Usage: required
0035 Value type: <string>
0036 Definition: Name of the PLL. Typically hfpllX where X is a CPU number
0037 starting at 0. Otherwise hfpll_Y where Y is more specific
0038 such as "l2".
0039
0040 Example:
0041
0042 1) An HFPLL for the L2 cache.
0043
0044 clock-controller@f9016000 {
0045 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
0046 reg = <0xf9016000 0x30>;
0047 clocks = <&xo_board>;
0048 clock-names = "xo";
0049 clock-output-names = "hfpll_l2";
0050 };
0051
0052 2) An HFPLL for CPU0. This HFPLL has the alias register region.
0053
0054 clock-controller@f908a000 {
0055 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
0056 reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
0057 clocks = <&xo_board>;
0058 clock-names = "xo";
0059 clock-output-names = "hfpll0";
0060 };
