0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Graphics Clock & Reset Controller Binding
0008
0009 maintainers:
0010 - Robert Foss <robert.foss@linaro.org>
0011
0012 description: |
0013 Qualcomm graphics clock control module which supports the clocks, resets and
0014 power domains on Qualcomm SoCs.
0015
0016 See also:
0017 dt-bindings/clock/qcom,gpucc-sm8350.h
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - qcom,sm8350-gpucc
0023
0024 clocks:
0025 items:
0026 - description: Board XO source
0027 - description: GPLL0 main branch source
0028 - description: GPLL0 div branch source
0029
0030 '#clock-cells':
0031 const: 1
0032
0033 '#reset-cells':
0034 const: 1
0035
0036 '#power-domain-cells':
0037 const: 1
0038
0039 reg:
0040 maxItems: 1
0041
0042 required:
0043 - compatible
0044 - reg
0045 - clocks
0046 - '#clock-cells'
0047 - '#reset-cells'
0048 - '#power-domain-cells'
0049
0050 additionalProperties: false
0051
0052 examples:
0053 - |
0054 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
0055 #include <dt-bindings/clock/qcom,rpmh.h>
0056
0057 soc {
0058 #address-cells = <2>;
0059 #size-cells = <2>;
0060
0061 clock-controller@3d90000 {
0062 compatible = "qcom,sm8350-gpucc";
0063 reg = <0 0x03d90000 0 0x9000>;
0064 clocks = <&rpmhcc RPMH_CXO_CLK>,
0065 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
0066 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
0067 #clock-cells = <1>;
0068 #reset-cells = <1>;
0069 #power-domain-cells = <1>;
0070 };
0071 };
0072 ...
