0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
0008
0009 maintainers:
0010 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
0011
0012 description: |
0013 Qualcomm graphics clock control module which supports the clocks, resets and
0014 power domains on SDM630 and SDM660.
0015
0016 See also dt-bindings/clock/qcom,gpucc-sdm660.h.
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - qcom,gpucc-sdm630
0022 - qcom,gpucc-sdm660
0023
0024 clocks:
0025 items:
0026 - description: Board XO source
0027 - description: GPLL0 main gpu branch
0028 - description: GPLL0 divider gpu branch
0029
0030 clock-names:
0031 items:
0032 - const: xo
0033 - const: gcc_gpu_gpll0_clk
0034 - const: gcc_gpu_gpll0_div_clk
0035
0036 '#clock-cells':
0037 const: 1
0038
0039 '#reset-cells':
0040 const: 1
0041
0042 '#power-domain-cells':
0043 const: 1
0044
0045 reg:
0046 maxItems: 1
0047
0048 required:
0049 - compatible
0050 - reg
0051 - clocks
0052 - clock-names
0053 - '#clock-cells'
0054 - '#reset-cells'
0055 - '#power-domain-cells'
0056
0057 additionalProperties: false
0058
0059 examples:
0060 - |
0061 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
0062 #include <dt-bindings/clock/qcom,rpmcc.h>
0063
0064 clock-controller@5065000 {
0065 compatible = "qcom,gpucc-sdm660";
0066 reg = <0x05065000 0x9038>;
0067 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
0068 <&gcc GCC_GPU_GPLL0_CLK>,
0069 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
0070 clock-names = "xo", "gcc_gpu_gpll0_clk",
0071 "gcc_gpu_gpll0_div_clk";
0072 #clock-cells = <1>;
0073 #power-domain-cells = <1>;
0074 #reset-cells = <1>;
0075 };
0076 ...
