0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Global Clock & Reset Controller Binding for SM8350
0008
0009 maintainers:
0010 - Vinod Koul <vkoul@kernel.org>
0011
0012 description: |
0013 Qualcomm global clock control module which supports the clocks, resets and
0014 power domains on SM8350.
0015
0016 See also:
0017 - dt-bindings/clock/qcom,gcc-sm8350.h
0018
0019 properties:
0020 compatible:
0021 const: qcom,gcc-sm8350
0022
0023 clocks:
0024 items:
0025 - description: Board XO source
0026 - description: Sleep clock source
0027 - description: PLL test clock source (Optional clock)
0028 - description: PCIE 0 Pipe clock source (Optional clock)
0029 - description: PCIE 1 Pipe clock source (Optional clock)
0030 - description: UFS card Rx symbol 0 clock source (Optional clock)
0031 - description: UFS card Rx symbol 1 clock source (Optional clock)
0032 - description: UFS card Tx symbol 0 clock source (Optional clock)
0033 - description: UFS phy Rx symbol 0 clock source (Optional clock)
0034 - description: UFS phy Rx symbol 1 clock source (Optional clock)
0035 - description: UFS phy Tx symbol 0 clock source (Optional clock)
0036 - description: USB3 phy wrapper pipe clock source (Optional clock)
0037 - description: USB3 phy sec pipe clock source (Optional clock)
0038 minItems: 2
0039
0040 clock-names:
0041 items:
0042 - const: bi_tcxo
0043 - const: sleep_clk
0044 - const: core_bi_pll_test_se # Optional clock
0045 - const: pcie_0_pipe_clk # Optional clock
0046 - const: pcie_1_pipe_clk # Optional clock
0047 - const: ufs_card_rx_symbol_0_clk # Optional clock
0048 - const: ufs_card_rx_symbol_1_clk # Optional clock
0049 - const: ufs_card_tx_symbol_0_clk # Optional clock
0050 - const: ufs_phy_rx_symbol_0_clk # Optional clock
0051 - const: ufs_phy_rx_symbol_1_clk # Optional clock
0052 - const: ufs_phy_tx_symbol_0_clk # Optional clock
0053 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
0054 - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
0055 minItems: 2
0056
0057 '#clock-cells':
0058 const: 1
0059
0060 '#reset-cells':
0061 const: 1
0062
0063 '#power-domain-cells':
0064 const: 1
0065
0066 reg:
0067 maxItems: 1
0068
0069 required:
0070 - compatible
0071 - clocks
0072 - clock-names
0073 - reg
0074 - '#clock-cells'
0075 - '#reset-cells'
0076 - '#power-domain-cells'
0077
0078 additionalProperties: false
0079
0080 examples:
0081 - |
0082 #include <dt-bindings/clock/qcom,rpmh.h>
0083 clock-controller@100000 {
0084 compatible = "qcom,gcc-sm8350";
0085 reg = <0x00100000 0x1f0000>;
0086 clocks = <&rpmhcc RPMH_CXO_CLK>,
0087 <&sleep_clk>;
0088 clock-names = "bi_tcxo", "sleep_clk";
0089 #clock-cells = <1>;
0090 #reset-cells = <1>;
0091 #power-domain-cells = <1>;
0092 };
0093
0094 ...
