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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Qualcomm Global Clock & Reset Controller Binding for SDX65
0008 
0009 maintainers:
0010   - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
0011 
0012 description: |
0013   Qualcomm global clock control module which supports the clocks, resets and
0014   power domains on SDX65
0015 
0016   See also:
0017   - dt-bindings/clock/qcom,gcc-sdx65.h
0018 
0019 properties:
0020   compatible:
0021     const: qcom,gcc-sdx65
0022 
0023   reg:
0024     maxItems: 1
0025 
0026   clocks:
0027     items:
0028       - description: Board XO source
0029       - description: Board active XO source
0030       - description: Sleep clock source
0031       - description: PCIE Pipe clock source
0032       - description: USB3 phy wrapper pipe clock source
0033       - description: PLL test clock source (Optional clock)
0034     minItems: 5
0035 
0036   clock-names:
0037     items:
0038       - const: bi_tcxo
0039       - const: bi_tcxo_ao
0040       - const: sleep_clk
0041       - const: pcie_pipe_clk
0042       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
0043       - const: core_bi_pll_test_se # Optional clock
0044     minItems: 5
0045 
0046   '#clock-cells':
0047     const: 1
0048 
0049   '#reset-cells':
0050     const: 1
0051 
0052   '#power-domain-cells':
0053     const: 1
0054 
0055 required:
0056   - compatible
0057   - reg
0058   - clocks
0059   - clock-names
0060   - '#clock-cells'
0061   - '#reset-cells'
0062   - '#power-domain-cells'
0063 
0064 additionalProperties: false
0065 
0066 examples:
0067   - |
0068     #include <dt-bindings/clock/qcom,rpmh.h>
0069     clock-controller@100000 {
0070       compatible = "qcom,gcc-sdx65";
0071       reg = <0x100000 0x1f7400>;
0072       clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
0073                <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
0074       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
0075                     "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
0076       #clock-cells = <1>;
0077       #reset-cells = <1>;
0078       #power-domain-cells = <1>;
0079     };
0080 ...