0001 # SPDX-License-Identifier: GPL-2.0-only
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Global Clock & Reset Controller Binding
0008
0009 maintainers:
0010 - Stephen Boyd <sboyd@kernel.org>
0011 - Taniya Das <tdas@codeaurora.org>
0012
0013 description: |
0014 Qualcomm global clock control module which supports the clocks, resets and
0015 power domains on SDM845
0016
0017 See also:
0018 - dt-bindings/clock/qcom,gcc-sdm845.h
0019
0020 properties:
0021 compatible:
0022 const: qcom,gcc-sdm845
0023
0024 clocks:
0025 items:
0026 - description: Board XO source
0027 - description: Board active XO source
0028 - description: Sleep clock source
0029 - description: PCIE 0 Pipe clock source
0030 - description: PCIE 1 Pipe clock source
0031
0032 clock-names:
0033 items:
0034 - const: bi_tcxo
0035 - const: bi_tcxo_ao
0036 - const: sleep_clk
0037 - const: pcie_0_pipe_clk
0038 - const: pcie_1_pipe_clk
0039
0040 '#clock-cells':
0041 const: 1
0042
0043 '#reset-cells':
0044 const: 1
0045
0046 power-domains:
0047 maxItems: 1
0048
0049 '#power-domain-cells':
0050 const: 1
0051
0052 reg:
0053 maxItems: 1
0054
0055 protected-clocks:
0056 description:
0057 Protected clock specifier list as per common clock binding.
0058
0059 required:
0060 - compatible
0061 - reg
0062 - '#clock-cells'
0063 - '#reset-cells'
0064 - '#power-domain-cells'
0065
0066 additionalProperties: false
0067
0068 examples:
0069 # Example for GCC for SDM845:
0070 - |
0071 #include <dt-bindings/clock/qcom,rpmh.h>
0072 clock-controller@100000 {
0073 compatible = "qcom,gcc-sdm845";
0074 reg = <0x100000 0x1f0000>;
0075 clocks = <&rpmhcc RPMH_CXO_CLK>,
0076 <&rpmhcc RPMH_CXO_CLK_A>,
0077 <&sleep_clk>,
0078 <&pcie0_lane>,
0079 <&pcie1_lane>;
0080 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
0081 #clock-cells = <1>;
0082 #reset-cells = <1>;
0083 #power-domain-cells = <1>;
0084 };
0085 ...
