0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description: |
0013 Qualcomm global clock control module which supports the clocks, resets and
0014 power domains on SC8280xp.
0015
0016 See also:
0017 - include/dt-bindings/clock/qcom,gcc-sc8280xp.h
0018
0019 properties:
0020 compatible:
0021 const: qcom,gcc-sc8280xp
0022
0023 clocks:
0024 items:
0025 - description: XO reference clock
0026 - description: Sleep clock
0027 - description: UFS memory first RX symbol clock
0028 - description: UFS memory second RX symbol clock
0029 - description: UFS memory first TX symbol clock
0030 - description: UFS card first RX symbol clock
0031 - description: UFS card second RX symbol clock
0032 - description: UFS card first TX symbol clock
0033 - description: Primary USB SuperSpeed pipe clock
0034 - description: USB4 PHY pipegmux clock source
0035 - description: USB4 PHY DP gmux clock source
0036 - description: USB4 PHY sys piegmux clock source
0037 - description: USB4 PHY PCIe pipe clock
0038 - description: USB4 PHY router max pipe clock
0039 - description: Primary USB4 RX0 clock
0040 - description: Primary USB4 RX1 clock
0041 - description: Secondary USB SuperSpeed pipe clock
0042 - description: Second USB4 PHY pipegmux clock source
0043 - description: Second USB4 PHY DP gmux clock source
0044 - description: Second USB4 PHY sys pipegmux clock source
0045 - description: Second USB4 PHY PCIe pipe clock
0046 - description: Second USB4 PHY router max pipe clock
0047 - description: Secondary USB4 RX0 clock
0048 - description: Secondary USB4 RX1 clock
0049 - description: Multiport USB first SupserSpeed pipe clock
0050 - description: Multiport USB second SuperSpeed pipe clock
0051 - description: PCIe 2a pipe clock
0052 - description: PCIe 2b pipe clock
0053 - description: PCIe 3a pipe clock
0054 - description: PCIe 3b pipe clock
0055 - description: PCIe 4 pipe clock
0056 - description: First EMAC controller reference clock
0057 - description: Second EMAC controller reference clock
0058
0059 '#clock-cells':
0060 const: 1
0061
0062 '#reset-cells':
0063 const: 1
0064
0065 '#power-domain-cells':
0066 const: 1
0067
0068 reg:
0069 maxItems: 1
0070
0071 protected-clocks:
0072 maxItems: 389
0073
0074 required:
0075 - compatible
0076 - clocks
0077 - reg
0078 - '#clock-cells'
0079 - '#reset-cells'
0080 - '#power-domain-cells'
0081
0082 additionalProperties: false
0083
0084 examples:
0085 - |
0086 #include <dt-bindings/clock/qcom,rpmh.h>
0087 clock-controller@100000 {
0088 compatible = "qcom,gcc-sc8280xp";
0089 reg = <0x00100000 0x1f0000>;
0090 clocks = <&rpmhcc RPMH_CXO_CLK>,
0091 <&sleep_clk>,
0092 <&ufs_phy_rx_symbol_0_clk>,
0093 <&ufs_phy_rx_symbol_1_clk>,
0094 <&ufs_phy_tx_symbol_0_clk>,
0095 <&ufs_card_rx_symbol_0_clk>,
0096 <&ufs_card_rx_symbol_1_clk>,
0097 <&ufs_card_tx_symbol_0_clk>,
0098 <&usb_0_ssphy>,
0099 <&gcc_usb4_phy_pipegmux_clk_src>,
0100 <&gcc_usb4_phy_dp_gmux_clk_src>,
0101 <&gcc_usb4_phy_sys_pipegmux_clk_src>,
0102 <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
0103 <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
0104 <&qusb4phy_gcc_usb4_rx0_clk>,
0105 <&qusb4phy_gcc_usb4_rx1_clk>,
0106 <&usb_1_ssphy>,
0107 <&gcc_usb4_1_phy_pipegmux_clk_src>,
0108 <&gcc_usb4_1_phy_dp_gmux_clk_src>,
0109 <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
0110 <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
0111 <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
0112 <&qusb4phy_1_gcc_usb4_rx0_clk>,
0113 <&qusb4phy_1_gcc_usb4_rx1_clk>,
0114 <&usb_2_ssphy>,
0115 <&usb_3_ssphy>,
0116 <&pcie2a_lane>,
0117 <&pcie2b_lane>,
0118 <&pcie3a_lane>,
0119 <&pcie3b_lane>,
0120 <&pcie4_lane>,
0121 <&rxc0_ref_clk>,
0122 <&rxc1_ref_clk>;
0123
0124 #clock-cells = <1>;
0125 #reset-cells = <1>;
0126 #power-domain-cells = <1>;
0127 };
0128 ...
