0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Global Clock & Reset Controller Binding for SC7280
0008
0009 maintainers:
0010 - Taniya Das <tdas@codeaurora.org>
0011
0012 description: |
0013 Qualcomm global clock control module which supports the clocks, resets and
0014 power domains on SC7280.
0015
0016 See also:
0017 - dt-bindings/clock/qcom,gcc-sc7280.h
0018
0019 properties:
0020 compatible:
0021 const: qcom,gcc-sc7280
0022
0023 clocks:
0024 items:
0025 - description: Board XO source
0026 - description: Board active XO source
0027 - description: Sleep clock source
0028 - description: PCIE-0 pipe clock source
0029 - description: PCIE-1 pipe clock source
0030 - description: USF phy rx symbol 0 clock source
0031 - description: USF phy rx symbol 1 clock source
0032 - description: USF phy tx symbol 0 clock source
0033 - description: USB30 phy wrapper pipe clock source
0034
0035 clock-names:
0036 items:
0037 - const: bi_tcxo
0038 - const: bi_tcxo_ao
0039 - const: sleep_clk
0040 - const: pcie_0_pipe_clk
0041 - const: pcie_1_pipe_clk
0042 - const: ufs_phy_rx_symbol_0_clk
0043 - const: ufs_phy_rx_symbol_1_clk
0044 - const: ufs_phy_tx_symbol_0_clk
0045 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
0046
0047 '#clock-cells':
0048 const: 1
0049
0050 '#reset-cells':
0051 const: 1
0052
0053 '#power-domain-cells':
0054 const: 1
0055
0056 reg:
0057 maxItems: 1
0058
0059 required:
0060 - compatible
0061 - clocks
0062 - clock-names
0063 - reg
0064 - '#clock-cells'
0065 - '#reset-cells'
0066 - '#power-domain-cells'
0067
0068 additionalProperties: false
0069
0070 examples:
0071 - |
0072 #include <dt-bindings/clock/qcom,rpmh.h>
0073 clock-controller@100000 {
0074 compatible = "qcom,gcc-sc7280";
0075 reg = <0x00100000 0x1f0000>;
0076 clocks = <&rpmhcc RPMH_CXO_CLK>,
0077 <&rpmhcc RPMH_CXO_CLK_A>,
0078 <&sleep_clk>,
0079 <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
0080 <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
0081 <&ufs_phy_tx_symbol_0_clk>,
0082 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
0083
0084 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
0085 "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
0086 "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
0087 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
0088 #clock-cells = <1>;
0089 #reset-cells = <1>;
0090 #power-domain-cells = <1>;
0091 };
0092 ...
