0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
0008
0009 maintainers:
0010 - Jonathan Marek <jonathan@marek.ca>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks, resets and
0014 power domains on SM8150/SM8250/SM8350.
0015
0016 See also:
0017 dt-bindings/clock/qcom,dispcc-sm8150.h
0018 dt-bindings/clock/qcom,dispcc-sm8250.h
0019 dt-bindings/clock/qcom,dispcc-sm8350.h
0020
0021 properties:
0022 compatible:
0023 enum:
0024 - qcom,sc8180x-dispcc
0025 - qcom,sm8150-dispcc
0026 - qcom,sm8250-dispcc
0027 - qcom,sm8350-dispcc
0028
0029 clocks:
0030 items:
0031 - description: Board XO source
0032 - description: Byte clock from DSI PHY0
0033 - description: Pixel clock from DSI PHY0
0034 - description: Byte clock from DSI PHY1
0035 - description: Pixel clock from DSI PHY1
0036 - description: Link clock from DP PHY
0037 - description: VCO DIV clock from DP PHY
0038
0039 clock-names:
0040 items:
0041 - const: bi_tcxo
0042 - const: dsi0_phy_pll_out_byteclk
0043 - const: dsi0_phy_pll_out_dsiclk
0044 - const: dsi1_phy_pll_out_byteclk
0045 - const: dsi1_phy_pll_out_dsiclk
0046 - const: dp_phy_pll_link_clk
0047 - const: dp_phy_pll_vco_div_clk
0048
0049 '#clock-cells':
0050 const: 1
0051
0052 '#reset-cells':
0053 const: 1
0054
0055 '#power-domain-cells':
0056 const: 1
0057
0058 reg:
0059 maxItems: 1
0060
0061 power-domains:
0062 description:
0063 A phandle and PM domain specifier for the MMCX power domain.
0064 maxItems: 1
0065
0066 required-opps:
0067 description:
0068 A phandle to an OPP node describing required MMCX performance point.
0069 maxItems: 1
0070
0071 required:
0072 - compatible
0073 - reg
0074 - clocks
0075 - clock-names
0076 - '#clock-cells'
0077 - '#reset-cells'
0078 - '#power-domain-cells'
0079
0080 additionalProperties: false
0081
0082 examples:
0083 - |
0084 #include <dt-bindings/clock/qcom,rpmh.h>
0085 #include <dt-bindings/power/qcom-rpmpd.h>
0086 clock-controller@af00000 {
0087 compatible = "qcom,sm8250-dispcc";
0088 reg = <0x0af00000 0x10000>;
0089 clocks = <&rpmhcc RPMH_CXO_CLK>,
0090 <&dsi0_phy 0>,
0091 <&dsi0_phy 1>,
0092 <&dsi1_phy 0>,
0093 <&dsi1_phy 1>,
0094 <&dp_phy 0>,
0095 <&dp_phy 1>;
0096 clock-names = "bi_tcxo",
0097 "dsi0_phy_pll_out_byteclk",
0098 "dsi0_phy_pll_out_dsiclk",
0099 "dsi1_phy_pll_out_byteclk",
0100 "dsi1_phy_pll_out_dsiclk",
0101 "dp_phy_pll_link_clk",
0102 "dp_phy_pll_vco_div_clk";
0103 #clock-cells = <1>;
0104 #reset-cells = <1>;
0105 #power-domain-cells = <1>;
0106 power-domains = <&rpmhpd SM8250_MMCX>;
0107 required-opps = <&rpmhpd_opp_low_svs>;
0108 };
0109 ...
