0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock & Reset Controller Binding for SM6350
0008
0009 maintainers:
0010 - Konrad Dybcio <konrad.dybcio@somainline.org>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks, resets and
0014 power domains on SM6350.
0015
0016 See also dt-bindings/clock/qcom,dispcc-sm6350.h.
0017
0018 properties:
0019 compatible:
0020 const: qcom,sm6350-dispcc
0021
0022 clocks:
0023 items:
0024 - description: Board XO source
0025 - description: GPLL0 source from GCC
0026 - description: Byte clock from DSI PHY
0027 - description: Pixel clock from DSI PHY
0028 - description: Link clock from DP PHY
0029 - description: VCO DIV clock from DP PHY
0030
0031 clock-names:
0032 items:
0033 - const: bi_tcxo
0034 - const: gcc_disp_gpll0_clk
0035 - const: dsi0_phy_pll_out_byteclk
0036 - const: dsi0_phy_pll_out_dsiclk
0037 - const: dp_phy_pll_link_clk
0038 - const: dp_phy_pll_vco_div_clk
0039
0040 '#clock-cells':
0041 const: 1
0042
0043 '#reset-cells':
0044 const: 1
0045
0046 '#power-domain-cells':
0047 const: 1
0048
0049 reg:
0050 maxItems: 1
0051
0052 required:
0053 - compatible
0054 - reg
0055 - clocks
0056 - clock-names
0057 - '#clock-cells'
0058 - '#reset-cells'
0059 - '#power-domain-cells'
0060
0061 additionalProperties: false
0062
0063 examples:
0064 - |
0065 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
0066 #include <dt-bindings/clock/qcom,rpmh.h>
0067 clock-controller@af00000 {
0068 compatible = "qcom,sm6350-dispcc";
0069 reg = <0x0af00000 0x20000>;
0070 clocks = <&rpmhcc RPMH_CXO_CLK>,
0071 <&gcc GCC_DISP_GPLL0_CLK>,
0072 <&dsi_phy 0>,
0073 <&dsi_phy 1>,
0074 <&dp_phy 0>,
0075 <&dp_phy 1>;
0076 clock-names = "bi_tcxo",
0077 "gcc_disp_gpll0_clk",
0078 "dsi0_phy_pll_out_byteclk",
0079 "dsi0_phy_pll_out_dsiclk",
0080 "dp_phy_pll_link_clk",
0081 "dp_phy_pll_vco_div_clk";
0082 #clock-cells = <1>;
0083 #reset-cells = <1>;
0084 #power-domain-cells = <1>;
0085 };
0086 ...
