0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm Display Clock Controller Binding for SM6125
0008
0009 maintainers:
0010 - Martin Botka <martin.botka@somainline.org>
0011
0012 description: |
0013 Qualcomm display clock control module which supports the clocks and
0014 power domains on SM6125.
0015
0016 See also:
0017 dt-bindings/clock/qcom,dispcc-sm6125.h
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - qcom,sm6125-dispcc
0023
0024 clocks:
0025 items:
0026 - description: Board XO source
0027 - description: Byte clock from DSI PHY0
0028 - description: Pixel clock from DSI PHY0
0029 - description: Pixel clock from DSI PHY1
0030 - description: Link clock from DP PHY
0031 - description: VCO DIV clock from DP PHY
0032 - description: AHB config clock from GCC
0033
0034 clock-names:
0035 items:
0036 - const: bi_tcxo
0037 - const: dsi0_phy_pll_out_byteclk
0038 - const: dsi0_phy_pll_out_dsiclk
0039 - const: dsi1_phy_pll_out_dsiclk
0040 - const: dp_phy_pll_link_clk
0041 - const: dp_phy_pll_vco_div_clk
0042 - const: cfg_ahb_clk
0043
0044 '#clock-cells':
0045 const: 1
0046
0047 '#power-domain-cells':
0048 const: 1
0049
0050 reg:
0051 maxItems: 1
0052
0053 required:
0054 - compatible
0055 - reg
0056 - clocks
0057 - clock-names
0058 - '#clock-cells'
0059 - '#power-domain-cells'
0060
0061 additionalProperties: false
0062
0063 examples:
0064 - |
0065 #include <dt-bindings/clock/qcom,rpmcc.h>
0066 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
0067 clock-controller@5f00000 {
0068 compatible = "qcom,sm6125-dispcc";
0069 reg = <0x5f00000 0x20000>;
0070 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
0071 <&dsi0_phy 0>,
0072 <&dsi0_phy 1>,
0073 <&dsi1_phy 1>,
0074 <&dp_phy 0>,
0075 <&dp_phy 1>,
0076 <&gcc GCC_DISP_AHB_CLK>;
0077 clock-names = "bi_tcxo",
0078 "dsi0_phy_pll_out_byteclk",
0079 "dsi0_phy_pll_out_dsiclk",
0080 "dsi1_phy_pll_out_dsiclk",
0081 "dp_phy_pll_link_clk",
0082 "dp_phy_pll_vco_div_clk",
0083 "cfg_ahb_clk";
0084 #clock-cells = <1>;
0085 #power-domain-cells = <1>;
0086 };
0087 ...
