0001 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
0002
0003 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
0004
0005 Required Properties:
0006 - compatible: has to be "qca,<soctype>-pll" and one of the following
0007 fallbacks:
0008 - "qca,ar7100-pll"
0009 - "qca,ar7240-pll"
0010 - "qca,ar9130-pll"
0011 - "qca,ar9330-pll"
0012 - "qca,ar9340-pll"
0013 - "qca,qca9550-pll"
0014 - reg: Base address and size of the controllers memory area
0015 - clock-names: Name of the input clock, has to be "ref"
0016 - clocks: phandle of the external reference clock
0017 - #clock-cells: has to be one
0018
0019 Optional properties:
0020 - clock-output-names: should be "cpu", "ddr", "ahb"
0021
0022 Example:
0023
0024 pll-controller@18050000 {
0025 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
0026 reg = <0x18050000 0x20>;
0027
0028 clock-names = "ref";
0029 clocks = <&extosc>;
0030
0031 #clock-cells = <1>;
0032 clock-output-names = "cpu", "ddr", "ahb";
0033 };
