0001 Imagination Technologies Pistachio SoC clock controllers
0002 ========================================================
0003
0004 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
0005 general control, and top general control) which are instantiated individually
0006 from the device-tree.
0007
0008 External clocks:
0009 ----------------
0010
0011 There are three external inputs to the clock controllers which should be
0012 defined with the following clock-output-names:
0013 - "xtal": External 52Mhz oscillator (required)
0014 - "audio_clk_in": Alternate audio reference clock (optional)
0015 - "enet_clk_in": Alternate ethernet PHY clock (optional)
0016
0017 Core clock controller:
0018 ----------------------
0019
0020 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
0021 co-processor), audio, and several peripherals.
0022
0023 Required properties:
0024 - compatible: Must be "img,pistachio-clk".
0025 - reg: Must contain the base address and length of the core clock controller.
0026 - #clock-cells: Must be 1. The single cell is the clock identifier.
0027 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
0028 - clocks: Must contain an entry for each clock in clock-names.
0029 - clock-names: Must include "xtal" (see "External clocks") and
0030 "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
0031 top-level general control.
0032
0033 Example:
0034 clk_core: clock-controller@18144000 {
0035 compatible = "img,pistachio-clk";
0036 reg = <0x18144000 0x800>;
0037 clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
0038 <&cr_top EXT_CLK_ENET_IN>;
0039 clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
0040
0041 #clock-cells = <1>;
0042 };
0043
0044 Peripheral clock controller:
0045 ----------------------------
0046
0047 The peripheral clock controller generates clocks for the DDR, ROM, and other
0048 peripherals. The peripheral system clock ("periph_sys") generated by the core
0049 clock controller is the input clock to the peripheral clock controller.
0050
0051 Required properties:
0052 - compatible: Must be "img,pistachio-periph-clk".
0053 - reg: Must contain the base address and length of the peripheral clock
0054 controller.
0055 - #clock-cells: Must be 1. The single cell is the clock identifier.
0056 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
0057 - clocks: Must contain an entry for each clock in clock-names.
0058 - clock-names: Must include "periph_sys", the peripheral system clock generated
0059 by the core clock controller.
0060
0061 Example:
0062 clk_periph: clock-controller@18144800 {
0063 compatible = "img,pistachio-clk-periph";
0064 reg = <0x18144800 0x800>;
0065 clocks = <&clk_core CLK_PERIPH_SYS>;
0066 clock-names = "periph_sys";
0067
0068 #clock-cells = <1>;
0069 };
0070
0071 Peripheral general control:
0072 ---------------------------
0073
0074 The peripheral general control block generates system interface clocks and
0075 resets for various peripherals. It also contains miscellaneous peripheral
0076 control registers. The system clock ("sys") generated by the peripheral clock
0077 controller is the input clock to the system clock controller.
0078
0079 Required properties:
0080 - compatible: Must include "img,pistachio-periph-cr" and "syscon".
0081 - reg: Must contain the base address and length of the peripheral general
0082 control registers.
0083 - #clock-cells: Must be 1. The single cell is the clock identifier.
0084 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
0085 - clocks: Must contain an entry for each clock in clock-names.
0086 - clock-names: Must include "sys", the system clock generated by the peripheral
0087 clock controller.
0088
0089 Example:
0090 cr_periph: syscon@18144800 {
0091 compatible = "img,pistachio-cr-periph", "syscon";
0092 reg = <0x18148000 0x1000>;
0093 clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
0094 clock-names = "sys";
0095
0096 #clock-cells = <1>;
0097 };
0098
0099 Top-level general control:
0100 --------------------------
0101
0102 The top-level general control block contains miscellaneous control registers and
0103 gates for the external clocks "audio_clk_in" and "enet_clk_in".
0104
0105 Required properties:
0106 - compatible: Must include "img,pistachio-cr-top" and "syscon".
0107 - reg: Must contain the base address and length of the top-level
0108 control registers.
0109 - clocks: Must contain an entry for each clock in clock-names.
0110 - clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
0111 "External clocks").
0112 - #clock-cells: Must be 1. The single cell is the clock identifier.
0113 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
0114
0115 Example:
0116 cr_top: syscon@18144800 {
0117 compatible = "img,pistachio-cr-top", "syscon";
0118 reg = <0x18149000 0x200>;
0119 clocks = <&audio_refclk>, <&ext_enet_in>;
0120 clock-names = "audio_clk_in", "enet_clk_in";
0121
0122 #clock-cells = <1>;
0123 };
