bindings/clock/nvidia%2Ctegra20-car.yaml

0001 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Clock and Reset Controller
0008
0009 maintainers:
0010   - Jon Hunter <jonathanh@nvidia.com>
0011   - Thierry Reding <thierry.reding@gmail.com>
0012
0013 description: |
0014   The Clock and Reset (CAR) is the HW module responsible for muxing and gating
0015   Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
0016
0017   CLKGEN provides the registers to program the PLLs. It controls most of
0018   the clock source programming and most of the clock dividers.
0019
0020   CLKGEN input signals include the external clock for the reference frequency
0021   (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
0022
0023   Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
0024
0025   RSTGEN provides the registers needed to control resetting of each block in
0026   the Tegra system.
0027
0028 properties:
0029   compatible:
0030     enum:
0031       - nvidia,tegra20-car
0032       - nvidia,tegra30-car
0033       - nvidia,tegra114-car
0034       - nvidia,tegra210-car
0035
0036   reg:
0037     maxItems: 1
0038
0039   '#clock-cells':
0040     const: 1
0041
0042   "#reset-cells":
0043     const: 1
0044
0045 patternProperties:
0046   "^(sclk)|(pll-[cem])$":
0047     type: object
0048     properties:
0049       compatible:
0050         enum:
0051           - nvidia,tegra20-sclk
0052           - nvidia,tegra30-sclk
0053           - nvidia,tegra30-pllc
0054           - nvidia,tegra30-plle
0055           - nvidia,tegra30-pllm
0056
0057       operating-points-v2: true
0058
0059       clocks:
0060         items:
0061           - description: node's clock
0062
0063       power-domains:
0064         maxItems: 1
0065         description: phandle to the core SoC power domain
0066
0067     required:
0068       - compatible
0069       - operating-points-v2
0070       - clocks
0071       - power-domains
0072
0073     additionalProperties: false
0074
0075 required:
0076   - compatible
0077   - reg
0078   - '#clock-cells'
0079   - "#reset-cells"
0080
0081 additionalProperties: false
0082
0083 examples:
0084   - |
0085     #include <dt-bindings/clock/tegra20-car.h>
0086
0087     car: clock-controller@60006000 {
0088         compatible = "nvidia,tegra20-car";
0089         reg = <0x60006000 0x1000>;
0090         #clock-cells = <1>;
0091         #reset-cells = <1>;
0092
0093         sclk {
0094             compatible = "nvidia,tegra20-sclk";
0095             operating-points-v2 = <&opp_table>;
0096             clocks = <&tegra_car TEGRA20_CLK_SCLK>;
0097             power-domains = <&domain>;
0098         };
0099     };