0001 NVIDIA Tegra124 DFLL FCPU clocksource
0002
0003 This binding uses the common clock binding:
0004 Documentation/devicetree/bindings/clock/clock-bindings.txt
0005
0006 The DFLL IP block on Tegra is a root clocksource designed for clocking
0007 the fast CPU cluster. It consists of a free-running voltage controlled
0008 oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
0009 control module that will automatically adjust the VDD_CPU voltage by
0010 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
0011
0012 Required properties:
0013 - compatible : should be one of:
0014 - "nvidia,tegra124-dfll": for Tegra124
0015 - "nvidia,tegra210-dfll": for Tegra210
0016 - reg : Defines the following set of registers, in the order listed:
0017 - registers for the DFLL control logic.
0018 - registers for the I2C output logic.
0019 - registers for the integrated I2C master controller.
0020 - look-up table RAM for voltage register values.
0021 - interrupts: Should contain the DFLL block interrupt.
0022 - clocks: Must contain an entry for each entry in clock-names.
0023 See clock-bindings.txt for details.
0024 - clock-names: Must include the following entries:
0025 - soc: Clock source for the DFLL control logic.
0026 - ref: The closed loop reference clock
0027 - i2c: Clock source for the integrated I2C master.
0028 - resets: Must contain an entry for each entry in reset-names.
0029 See ../reset/reset.txt for details.
0030 - reset-names: Must include the following entries:
0031 - dvco: Reset control for the DFLL DVCO.
0032 - #clock-cells: Must be 0.
0033 - clock-output-names: Name of the clock output.
0034 - vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
0035 hardware will start controlling. The regulator will be queried for
0036 the I2C register, control values and supported voltages.
0037
0038 Required properties for the control loop parameters:
0039 - nvidia,sample-rate: Sample rate of the DFLL control loop.
0040 - nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
0041 - nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
0042 - nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
0043 - nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
0044 - nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
0045
0046 Optional properties for the control loop parameters:
0047 - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
0048
0049 Optional properties for mode selection:
0050 - nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
0051
0052 Required properties for I2C mode:
0053 - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
0054
0055 Required properties for PWM mode:
0056 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
0057 - nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
0058 control is disabled and the PWM output is tristated. Note that this voltage is
0059 configured in hardware, typically via a resistor divider.
0060 - nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
0061 is enabled and PWM output is low. Hence, this is the minimum output voltage
0062 that the regulator supports when PWM control is enabled.
0063 - nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
0064 corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
0065 duty cycle would be: nvidia,pwm-min-microvolts +
0066 nvidia,pwm-voltage-step-microvolts * 2.
0067 - pinctrl-0: I/O pad configuration when PWM control is enabled.
0068 - pinctrl-1: I/O pad configuration when PWM control is disabled.
0069 - pinctrl-names: must include the following entries:
0070 - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
0071 - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
0072
0073 Example for I2C:
0074
0075 clock@70110000 {
0076 compatible = "nvidia,tegra124-dfll";
0077 reg = <0 0x70110000 0 0x100>, /* DFLL control */
0078 <0 0x70110000 0 0x100>, /* I2C output control */
0079 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
0080 <0 0x70110200 0 0x100>; /* Look-up table RAM */
0081 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0082 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
0083 <&tegra_car TEGRA124_CLK_DFLL_REF>,
0084 <&tegra_car TEGRA124_CLK_I2C5>;
0085 clock-names = "soc", "ref", "i2c";
0086 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
0087 reset-names = "dvco";
0088 #clock-cells = <0>;
0089 clock-output-names = "dfllCPU_out";
0090 vdd-cpu-supply = <&vdd_cpu>;
0091
0092 nvidia,sample-rate = <12500>;
0093 nvidia,droop-ctrl = <0x00000f00>;
0094 nvidia,force-mode = <1>;
0095 nvidia,cf = <10>;
0096 nvidia,ci = <0>;
0097 nvidia,cg = <2>;
0098
0099 nvidia,i2c-fs-rate = <400000>;
0100 };
0101
0102 Example for PWM:
0103
0104 clock@70110000 {
0105 compatible = "nvidia,tegra124-dfll";
0106 reg = <0 0x70110000 0 0x100>, /* DFLL control */
0107 <0 0x70110000 0 0x100>, /* I2C output control */
0108 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
0109 <0 0x70110200 0 0x100>; /* Look-up table RAM */
0110 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0111 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
0112 <&tegra_car TEGRA210_CLK_DFLL_REF>,
0113 <&tegra_car TEGRA124_CLK_I2C5>;;
0114 clock-names = "soc", "ref", "i2c";
0115 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
0116 reset-names = "dvco";
0117 #clock-cells = <0>;
0118 clock-output-names = "dfllCPU_out";
0119
0120 nvidia,sample-rate = <25000>;
0121 nvidia,droop-ctrl = <0x00000f00>;
0122 nvidia,force-mode = <1>;
0123 nvidia,cf = <6>;
0124 nvidia,ci = <0>;
0125 nvidia,cg = <2>;
0126
0127 nvidia,pwm-min-microvolts = <708000>; /* 708mV */
0128 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
0129 nvidia,pwm-to-pmic;
0130 nvidia,pwm-tristate-microvolts = <1000000>;
0131 nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
0132
0133 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
0134 pinctrl-0 = <&dvfs_pwm_active_state>;
0135 pinctrl-1 = <&dvfs_pwm_inactive_state>;
0136 };
0137
0138 /* pinmux nodes added for completeness. Binding doc can be found in:
0139 * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
0140 */
0141
0142 pinmux: pinmux@700008d4 {
0143 dvfs_pwm_active_state: dvfs_pwm_active {
0144 dvfs_pwm_pbb1 {
0145 nvidia,pins = "dvfs_pwm_pbb1";
0146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0147 };
0148 };
0149 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
0150 dvfs_pwm_pbb1 {
0151 nvidia,pins = "dvfs_pwm_pbb1";
0152 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0153 };
0154 };
0155 };
