0001 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra Clock and Reset Controller
0008
0009 maintainers:
0010 - Jon Hunter <jonathanh@nvidia.com>
0011 - Thierry Reding <thierry.reding@gmail.com>
0012
0013 description: |
0014 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
0015 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
0016
0017 CLKGEN provides the registers to program the PLLs. It controls most of
0018 the clock source programming and most of the clock dividers.
0019
0020 CLKGEN input signals include the external clock for the reference frequency
0021 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
0022
0023 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
0024
0025 RSTGEN provides the registers needed to control resetting of each block in
0026 the Tegra system.
0027
0028 properties:
0029 compatible:
0030 const: nvidia,tegra124-car
0031
0032 reg:
0033 maxItems: 1
0034
0035 '#clock-cells':
0036 const: 1
0037
0038 "#reset-cells":
0039 const: 1
0040
0041 nvidia,external-memory-controller:
0042 $ref: /schemas/types.yaml#/definitions/phandle
0043 description:
0044 phandle of the external memory controller node
0045
0046 patternProperties:
0047 "^emc-timings-[0-9]+$":
0048 type: object
0049 properties:
0050 nvidia,ram-code:
0051 $ref: /schemas/types.yaml#/definitions/uint32
0052 description:
0053 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
0054 this timing set is used for
0055
0056 patternProperties:
0057 "^timing-[0-9]+$":
0058 type: object
0059 properties:
0060 clock-frequency:
0061 description:
0062 external memory clock rate in Hz
0063 minimum: 1000000
0064 maximum: 1000000000
0065
0066 nvidia,parent-clock-frequency:
0067 $ref: /schemas/types.yaml#/definitions/uint32
0068 description:
0069 rate of parent clock in Hz
0070 minimum: 1000000
0071 maximum: 1000000000
0072
0073 clocks:
0074 items:
0075 - description: parent clock of EMC
0076
0077 clock-names:
0078 items:
0079 - const: emc-parent
0080
0081 required:
0082 - clock-frequency
0083 - nvidia,parent-clock-frequency
0084 - clocks
0085 - clock-names
0086
0087 additionalProperties: false
0088
0089 additionalProperties: false
0090
0091 required:
0092 - compatible
0093 - reg
0094 - '#clock-cells'
0095 - "#reset-cells"
0096
0097 additionalProperties: false
0098
0099 examples:
0100 - |
0101 #include <dt-bindings/clock/tegra124-car.h>
0102
0103 car: clock-controller@60006000 {
0104 compatible = "nvidia,tegra124-car";
0105 reg = <0x60006000 0x1000>;
0106 #clock-cells = <1>;
0107 #reset-cells = <1>;
0108 };
