0001 * Core Clock bindings for Marvell MVEBU SoCs
0002
0003 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
0004 reading the Sample-At-Reset (SAR) register. The core clock consumer should
0005 specify the desired clock by having the clock ID in its "clocks" phandle cell.
0006
0007 The following is a list of provided IDs and clock names on Armada 370/XP:
0008 0 = tclk (Internal Bus clock)
0009 1 = cpuclk (CPU clock)
0010 2 = nbclk (L2 Cache clock)
0011 3 = hclk (DRAM control clock)
0012 4 = dramclk (DDR clock)
0013
0014 The following is a list of provided IDs and clock names on Armada 375:
0015 0 = tclk (Internal Bus clock)
0016 1 = cpuclk (CPU clock)
0017 2 = l2clk (L2 Cache clock)
0018 3 = ddrclk (DDR clock)
0019
0020 The following is a list of provided IDs and clock names on Armada 380/385:
0021 0 = tclk (Internal Bus clock)
0022 1 = cpuclk (CPU clock)
0023 2 = l2clk (L2 Cache clock)
0024 3 = ddrclk (DDR clock)
0025
0026 The following is a list of provided IDs and clock names on Armada 39x:
0027 0 = tclk (Internal Bus clock)
0028 1 = cpuclk (CPU clock)
0029 2 = nbclk (Coherent Fabric clock)
0030 3 = hclk (SDRAM Controller Internal Clock)
0031 4 = dclk (SDRAM Interface Clock)
0032 5 = refclk (Reference Clock)
0033
0034 The following is a list of provided IDs and clock names on 98dx3236:
0035 0 = tclk (Internal Bus clock)
0036 1 = cpuclk (CPU clock)
0037 2 = ddrclk (DDR clock)
0038 3 = mpll (MPLL Clock)
0039
0040 The following is a list of provided IDs and clock names on Kirkwood and Dove:
0041 0 = tclk (Internal Bus clock)
0042 1 = cpuclk (CPU0 clock)
0043 2 = l2clk (L2 Cache clock derived from CPU0 clock)
0044 3 = ddrclk (DDR controller clock derived from CPU0 clock)
0045
0046 The following is a list of provided IDs and clock names on Orion5x:
0047 0 = tclk (Internal Bus clock)
0048 1 = cpuclk (CPU0 clock)
0049 2 = ddrclk (DDR controller clock derived from CPU0 clock)
0050
0051 Required properties:
0052 - compatible : shall be one of the following:
0053 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
0054 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
0055 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
0056 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
0057 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
0058 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
0059 "marvell,dove-core-clock" - for Dove SoC core clocks
0060 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
0061 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
0062 "marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
0063 "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
0064 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
0065 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
0066 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
0067 - reg : shall be the register address of the Sample-At-Reset (SAR) register
0068 - #clock-cells : from common clock binding; shall be set to 1
0069
0070 Optional properties:
0071 - clock-output-names : from common clock binding; allows overwrite default clock
0072 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
0073
0074 Example:
0075
0076 core_clk: core-clocks@d0214 {
0077 compatible = "marvell,dove-core-clock";
0078 reg = <0xd0214 0x4>;
0079 #clock-cells = <1>;
0080 };
0081
0082 spi0: spi@10600 {
0083 compatible = "marvell,orion-spi";
0084 /* ... */
0085 /* get tclk from core clock provider */
0086 clocks = <&core_clk 0>;
0087 };
