0001 Device Tree Clock bindings for arch-moxart
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 MOXA ART SoCs allow to determine PLL output and APB frequencies
0008 by reading registers holding multiplier and divisor information.
0009
0010
0011 PLL:
0012
0013 Required properties:
0014 - compatible : Must be "moxa,moxart-pll-clock"
0015 - #clock-cells : Should be 0
0016 - reg : Should contain registers location and length
0017 - clocks : Should contain phandle + clock-specifier for the parent clock
0018
0019 Optional properties:
0020 - clock-output-names : Should contain clock name
0021
0022
0023 APB:
0024
0025 Required properties:
0026 - compatible : Must be "moxa,moxart-apb-clock"
0027 - #clock-cells : Should be 0
0028 - reg : Should contain registers location and length
0029 - clocks : Should contain phandle + clock-specifier for the parent clock
0030
0031 Optional properties:
0032 - clock-output-names : Should contain clock name
0033
0034
0035 For example:
0036
0037 clk_pll: clk_pll@98100000 {
0038 compatible = "moxa,moxart-pll-clock";
0039 #clock-cells = <0>;
0040 reg = <0x98100000 0x34>;
0041 };
0042
0043 clk_apb: clk_apb@98100000 {
0044 compatible = "moxa,moxart-apb-clock";
0045 #clock-cells = <0>;
0046 reg = <0x98100000 0x34>;
0047 clocks = <&clk_pll>;
0048 };
