0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip Sparx5 DPLL Clock
0008
0009 maintainers:
0010 - Lars Povlsen <lars.povlsen@microchip.com>
0011
0012 description: |
0013 The Sparx5 DPLL clock controller generates and supplies clock to
0014 various peripherals within the SoC.
0015
0016 properties:
0017 compatible:
0018 const: microchip,sparx5-dpll
0019
0020 reg:
0021 maxItems: 1
0022
0023 clocks:
0024 maxItems: 1
0025
0026 '#clock-cells':
0027 const: 1
0028
0029 required:
0030 - compatible
0031 - reg
0032 - clocks
0033 - '#clock-cells'
0034
0035 additionalProperties: false
0036
0037 examples:
0038 # Clock provider for eMMC:
0039 - |
0040 lcpll_clk: lcpll-clk {
0041 compatible = "fixed-clock";
0042 #clock-cells = <0>;
0043 clock-frequency = <2500000000>;
0044 };
0045 clks: clock-controller@61110000c {
0046 compatible = "microchip,sparx5-dpll";
0047 #clock-cells = <1>;
0048 clocks = <&lcpll_clk>;
0049 reg = <0x1110000c 0x24>;
0050 };
0051
0052 ...
