0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip PolarFire Clock Control Module Binding
0008
0009 maintainers:
0010 - Daire McNamara <daire.mcnamara@microchip.com>
0011
0012 description: |
0013 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
0014 which gates and enables all peripheral clocks.
0015
0016 This device tree binding describes 33 gate clocks. Clocks are referenced by
0017 user nodes by the CLKCFG node phandle and the clock index in the group, from
0018 0 to 32.
0019
0020 properties:
0021 compatible:
0022 const: microchip,mpfs-clkcfg
0023
0024 reg:
0025 items:
0026 - description: |
0027 clock config registers:
0028 These registers contain enable, reset & divider tables for the, cpu,
0029 axi, ahb and rtc/mtimer reference clocks as well as enable and reset
0030 for the peripheral clocks.
0031 - description: |
0032 mss pll dri registers:
0033 Block of registers responsible for dynamic reconfiguration of the mss
0034 pll
0035
0036 clocks:
0037 maxItems: 1
0038
0039 '#clock-cells':
0040 const: 1
0041 description: |
0042 The clock consumer should specify the desired clock by having the clock
0043 ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
0044 for the full list of PolarFire clock IDs.
0045
0046 required:
0047 - compatible
0048 - reg
0049 - clocks
0050 - '#clock-cells'
0051
0052 additionalProperties: false
0053
0054 examples:
0055 # Clock Config node:
0056 - |
0057 #include <dt-bindings/clock/microchip,mpfs-clock.h>
0058 soc {
0059 #address-cells = <2>;
0060 #size-cells = <2>;
0061 clkcfg: clock-controller@20002000 {
0062 compatible = "microchip,mpfs-clkcfg";
0063 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
0064 clocks = <&ref>;
0065 #clock-cells = <1>;
0066 };
0067 };
