0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip LAN966X Generic Clock Controller
0008
0009 maintainers:
0010 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
0011
0012 description: |
0013 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
0014 ddr_clk and sys_clk. This clock controller generates and supplies
0015 clock to various peripherals within the SoC.
0016
0017 properties:
0018 compatible:
0019 const: microchip,lan966x-gck
0020
0021 reg:
0022 minItems: 1
0023 items:
0024 - description: Generic clock registers
0025 - description: Optional gate clock registers
0026
0027 clocks:
0028 items:
0029 - description: CPU clock source
0030 - description: DDR clock source
0031 - description: System clock source
0032
0033 clock-names:
0034 items:
0035 - const: cpu
0036 - const: ddr
0037 - const: sys
0038
0039 '#clock-cells':
0040 const: 1
0041
0042 required:
0043 - compatible
0044 - reg
0045 - clocks
0046 - clock-names
0047 - '#clock-cells'
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 clks: clock-controller@e00c00a8 {
0054 compatible = "microchip,lan966x-gck";
0055 #clock-cells = <1>;
0056 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
0057 clock-names = "cpu", "ddr", "sys";
0058 reg = <0xe00c00a8 0x38>;
0059 };
0060 ...
