0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MT7621 Clock Device Tree Bindings
0008
0009 maintainers:
0010 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
0011
0012 description: |
0013 The MT7621 has a PLL controller from where the cpu clock is provided
0014 as well as derived clocks for the bus and the peripherals. It also
0015 can gate SoC device clocks.
0016
0017 Each clock is assigned an identifier and client nodes use this identifier
0018 to specify the clock which they consume.
0019
0020 All these identifiers could be found in:
0021 [1]: <include/dt-bindings/clock/mt7621-clk.h>.
0022
0023 The clocks are provided inside a system controller node.
0024
0025 This node is also a reset provider for all the peripherals.
0026
0027 Reset related bits are defined in:
0028 [2]: <include/dt-bindings/reset/mt7621-reset.h>.
0029
0030 properties:
0031 compatible:
0032 items:
0033 - const: mediatek,mt7621-sysc
0034 - const: syscon
0035
0036 reg:
0037 maxItems: 1
0038
0039 "#clock-cells":
0040 description:
0041 The first cell indicates the clock number, see [1] for available
0042 clocks.
0043 const: 1
0044
0045 "#reset-cells":
0046 description:
0047 The first cell indicates the reset bit within the register, see
0048 [2] for available resets.
0049 const: 1
0050
0051 ralink,memctl:
0052 $ref: /schemas/types.yaml#/definitions/phandle
0053 description:
0054 phandle of syscon used to control memory registers
0055
0056 clock-output-names:
0057 maxItems: 8
0058
0059 required:
0060 - compatible
0061 - reg
0062 - '#clock-cells'
0063 - ralink,memctl
0064
0065 additionalProperties: false
0066
0067 examples:
0068 - |
0069 #include <dt-bindings/clock/mt7621-clk.h>
0070
0071 sysc: sysc@0 {
0072 compatible = "mediatek,mt7621-sysc", "syscon";
0073 reg = <0x0 0x100>;
0074 #clock-cells = <1>;
0075 #reset-cells = <1>;
0076 ralink,memctl = <&memc>;
0077 clock-output-names = "xtal", "cpu", "bus",
0078 "50m", "125m", "150m",
0079 "250m", "270m";
0080 };
