0001 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
0002
0003 This device exposes 4 clocks in total:
0004
0005 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
0006 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
0007 frequencies
0008 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
0009
0010 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
0011 requests.
0012
0013 Required properties:
0014 - compatible: "maxim,max9485"
0015 - clocks: Input clock, must provice 27.000 MHz
0016 - clock-names: Must be set to "xclk"
0017 - #clock-cells: From common clock binding; shall be set to 1
0018
0019 Optional properties:
0020 - reset-gpios: GPIO descriptor connected to the #RESET input pin
0021 - vdd-supply: A regulator node for Vdd
0022 - clock-output-names: Name of output clocks, as defined in common clock
0023 bindings
0024
0025 If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
0026 and "clkout2".
0027
0028 Clocks are defined as preprocessor macros in the dt-binding header.
0029
0030 Example:
0031
0032 #include <dt-bindings/clock/maxim,max9485.h>
0033
0034 xo-27mhz: xo-27mhz {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <27000000>;
0038 };
0039
0040 &i2c0 {
0041 max9485: audio-clock@63 {
0042 reg = <0x63>;
0043 compatible = "maxim,max9485";
0044 clock-names = "xclk";
0045 clocks = <&xo-27mhz>;
0046 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
0047 vdd-supply = <&3v3-reg>;
0048 #clock-cells = <1>;
0049 };
0050 };
0051
0052 // Clock consumer node
0053
0054 foo@0 {
0055 compatible = "bar,foo";
0056 /* ... */
0057 clock-names = "foo-input-clk";
0058 clocks = <&max9485 MAX9485_CLKOUT1>;
0059 };
