0001 * Marvell PXA1928 Clock Controllers
0002
0003 The PXA1928 clock subsystem generates and supplies clock to various
0004 controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
0005 blocks called APMU, MPMU, and APBC roughly corresponding to internal buses.
0006
0007 Required Properties:
0008
0009 - compatible: should be one of the following.
0010 - "marvell,pxa1928-apmu" - APMU controller compatible
0011 - "marvell,pxa1928-mpmu" - MPMU controller compatible
0012 - "marvell,pxa1928-apbc" - APBC controller compatible
0013 - reg: physical base address of the clock controller and length of memory mapped
0014 region.
0015 - #clock-cells: should be 1.
0016 - #reset-cells: should be 1.
0017
0018 Each clock is assigned an identifier and client nodes use the clock controller
0019 phandle and this identifier to specify the clock which they consume.
0020
0021 All these identifiers can be found in <dt-bindings/clock/marvell,pxa1928.h>.
