0001 Device Tree Clock bindings for Marvell Berlin
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 Clock related registers are spread among the chip control registers. Berlin
0008 clock node should be a sub-node of the chip controller node. Marvell Berlin2
0009 (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
0010 minor differences in features and register layout.
0011
0012 Required properties:
0013 - compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
0014 - #clock-cells: must be 1
0015 - clocks: must be the input parent clock phandle
0016 - clock-names: name of the input parent clock
0017 Allowed clock-names for the reference clocks are
0018 "refclk" for the SoCs oscillator input on all SoCs,
0019 and SoC-specific input clocks for
0020 BG2/BG2CD: "video_ext0" for the external video clock input
0021
0022
0023 Example:
0024
0025 chip_clk: clock {
0026 compatible = "marvell,berlin2q-clk";
0027
0028 #clock-cells = <1>;
0029 clocks = <&refclk>;
0030 clock-names = "refclk";
0031 };
