0001 * NXP LPC1850 CREG clocks
0002
0003 The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
0004 control registers for two low speed clocks. One of the clocks is a
0005 32 kHz oscillator driver with power up/down and clock gating. Next
0006 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
0007
0008 These clocks are used by the RTC and the Event Router peripherials.
0009 The 32 kHz can also be routed to other peripherials to enable low
0010 power modes.
0011
0012 This binding uses the common clock binding:
0013 Documentation/devicetree/bindings/clock/clock-bindings.txt
0014
0015 Required properties:
0016 - compatible:
0017 Should be "nxp,lpc1850-creg-clk"
0018 - #clock-cells:
0019 Shall have value <1>.
0020 - clocks:
0021 Shall contain a phandle to the fixed 32 kHz crystal.
0022
0023 The creg-clk node must be a child of the creg syscon node.
0024
0025 The following clocks are available from the clock node.
0026
0027 Clock ID Name
0028 0 1 kHz clock
0029 1 32 kHz Oscillator
0030
0031 Example:
0032 soc {
0033 creg: syscon@40043000 {
0034 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
0035 reg = <0x40043000 0x1000>;
0036
0037 creg_clk: clock-controller {
0038 compatible = "nxp,lpc1850-creg-clk";
0039 clocks = <&xtal32>;
0040 #clock-cells = <1>;
0041 };
0042
0043 ...
0044 };
0045
0046 rtc: rtc@40046000 {
0047 ...
0048 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
0049 clock-names = "rtc", "reg";
0050 ...
0051 };
0052 };
