0001 * NXP LPC1850 Clock Generation Unit (CGU)
0002
0003 The CGU generates multiple independent clocks for the core and the
0004 peripheral blocks of the LPC18xx. Each independent clock is called
0005 a base clock and itself is one of the inputs to the two Clock
0006 Control Units (CCUs) which control the branch clocks to the
0007 individual peripherals.
0008
0009 The CGU selects the inputs to the clock generators from multiple
0010 clock sources, controls the clock generation, and routes the outputs
0011 of the clock generators through the clock source bus to the output
0012 stages. Each output stage provides an independent clock source and
0013 corresponds to one of the base clocks for the LPC18xx.
0014
0015 - Above text taken from NXP LPC1850 User Manual.
0016
0017
0018 This binding uses the common clock binding:
0019 Documentation/devicetree/bindings/clock/clock-bindings.txt
0020
0021 Required properties:
0022 - compatible:
0023 Should be "nxp,lpc1850-cgu"
0024 - reg:
0025 Shall define the base and range of the address space
0026 containing clock control registers
0027 - #clock-cells:
0028 Shall have value <1>. The permitted clock-specifier values
0029 are the base clock numbers defined below.
0030 - clocks:
0031 Shall contain a list of phandles for the external input
0032 sources to the CGU. The list shall be in the following
0033 order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
0034 - clock-indices:
0035 Shall be an ordered list of numbers defining the base clock
0036 number provided by the CGU.
0037 - clock-output-names:
0038 Shall be an ordered list of strings defining the names of
0039 the clocks provided by the CGU.
0040
0041 Which base clocks that are available on the CGU depends on the
0042 specific LPC part. Base clocks are numbered from 0 to 27.
0043
0044 Number: Name: Description:
0045 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
0046 1 BASE_USB0_CLK Base clock for USB0
0047 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
0048 SPI, and SGPIO
0049 3 BASE_USB1_CLK Base clock for USB1
0050 4 BASE_CPU_CLK System base clock for ARM Cortex-M core
0051 and APB peripheral blocks #0 and #2
0052 5 BASE_SPIFI_CLK Base clock for SPIFI
0053 6 BASE_SPI_CLK Base clock for SPI
0054 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
0055 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
0056 9 BASE_APB1_CLK Base clock for APB peripheral block # 1
0057 10 BASE_APB3_CLK Base clock for APB peripheral block # 3
0058 11 BASE_LCD_CLK Base clock for LCD
0059 12 BASE_ADCHS_CLK Base clock for ADCHS
0060 13 BASE_SDIO_CLK Base clock for SD/MMC
0061 14 BASE_SSP0_CLK Base clock for SSP0
0062 15 BASE_SSP1_CLK Base clock for SSP1
0063 16 BASE_UART0_CLK Base clock for UART0
0064 17 BASE_UART1_CLK Base clock for UART1
0065 18 BASE_UART2_CLK Base clock for UART2
0066 19 BASE_UART3_CLK Base clock for UART3
0067 20 BASE_OUT_CLK Base clock for CLKOUT pin
0068 24-21 - Reserved
0069 25 BASE_AUDIO_CLK Base clock for audio system (I2S)
0070 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
0071 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
0072
0073 BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
0074 BASE_ADCHS_CLK is only available on LPC4370.
0075
0076
0077 Example board file:
0078
0079 / {
0080 clocks {
0081 xtal: xtal {
0082 compatible = "fixed-clock";
0083 #clock-cells = <0>;
0084 clock-frequency = <12000000>;
0085 };
0086
0087 xtal32: xtal32 {
0088 compatible = "fixed-clock";
0089 #clock-cells = <0>;
0090 clock-frequency = <32768>;
0091 };
0092
0093 enet_rx_clk: enet_rx_clk {
0094 compatible = "fixed-clock";
0095 #clock-cells = <0>;
0096 clock-frequency = <0>;
0097 clock-output-names = "enet_rx_clk";
0098 };
0099
0100 enet_tx_clk: enet_tx_clk {
0101 compatible = "fixed-clock";
0102 #clock-cells = <0>;
0103 clock-frequency = <0>;
0104 clock-output-names = "enet_tx_clk";
0105 };
0106
0107 gp_clkin: gp_clkin {
0108 compatible = "fixed-clock";
0109 #clock-cells = <0>;
0110 clock-frequency = <0>;
0111 clock-output-names = "gp_clkin";
0112 };
0113 };
0114
0115 soc {
0116 cgu: clock-controller@40050000 {
0117 compatible = "nxp,lpc1850-cgu";
0118 reg = <0x40050000 0x1000>;
0119 #clock-cells = <1>;
0120 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
0121 };
0122
0123 /* A CGU and CCU clock consumer */
0124 lcdc: lcdc@40008000 {
0125 ...
0126 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
0127 clock-names = "clcdclk", "apb_pclk";
0128 ...
0129 };
0130 };
0131 };
