0001 * NXP LPC1850 Clock Control Unit (CCU)
0002
0003 Each CGU base clock has several clock branches which can be turned on
0004 or off independently by the Clock Control Units CCU1 or CCU2. The
0005 branch clocks are distributed between CCU1 and CCU2.
0006
0007 - Above text taken from NXP LPC1850 User Manual.
0008
0009 This binding uses the common clock binding:
0010 Documentation/devicetree/bindings/clock/clock-bindings.txt
0011
0012 Required properties:
0013 - compatible:
0014 Should be "nxp,lpc1850-ccu"
0015 - reg:
0016 Shall define the base and range of the address space
0017 containing clock control registers
0018 - #clock-cells:
0019 Shall have value <1>. The permitted clock-specifier values
0020 are the branch clock names defined in table below.
0021 - clocks:
0022 Shall contain a list of phandles for the base clocks routed
0023 from the CGU to the specific CCU. See mapping of base clocks
0024 and CCU in table below.
0025 - clock-names:
0026 Shall contain a list of names for the base clock routed
0027 from the CGU to the specific CCU. Valid CCU clock names:
0028 "base_usb0_clk", "base_periph_clk", "base_usb1_clk",
0029 "base_cpu_clk", "base_spifi_clk", "base_spi_clk",
0030 "base_apb1_clk", "base_apb3_clk", "base_adchs_clk",
0031 "base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk",
0032 "base_uart0_clk", "base_uart1_clk", "base_uart2_clk",
0033 "base_uart3_clk", "base_audio_clk"
0034
0035 Which branch clocks that are available on the CCU depends on the
0036 specific LPC part. Check the user manual for your specific part.
0037
0038 A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
0039
0040 Example board file:
0041
0042 soc {
0043 ccu1: clock-controller@40051000 {
0044 compatible = "nxp,lpc1850-ccu";
0045 reg = <0x40051000 0x1000>;
0046 #clock-cells = <1>;
0047 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
0048 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
0049 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
0050 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
0051 clock-names = "base_apb3_clk", "base_apb1_clk",
0052 "base_spifi_clk", "base_cpu_clk",
0053 "base_periph_clk", "base_usb0_clk",
0054 "base_usb1_clk", "base_spi_clk";
0055 };
0056
0057 ccu2: clock-controller@40052000 {
0058 compatible = "nxp,lpc1850-ccu";
0059 reg = <0x40052000 0x1000>;
0060 #clock-cells = <1>;
0061 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
0062 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
0063 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
0064 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
0065 clock-names = "base_audio_clk", "base_uart3_clk",
0066 "base_uart2_clk", "base_uart1_clk",
0067 "base_uart0_clk", "base_ssp1_clk",
0068 "base_ssp0_clk", "base_sdio_clk";
0069 };
0070
0071 /* A user of CCU brach clocks */
0072 uart1: serial@40082000 {
0073 ...
0074 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
0075 ...
0076 };
0077 };
