bindings/clock/imx8ulp-pcc-clock.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
0008
0009 maintainers:
0010   - Jacky Bai <ping.bai@nxp.com>
0011
0012 description: |
0013   On i.MX8ULP, The clock sources generation, distribution and management is
0014   under the control of several CGCs & PCCs modules. The PCC modules control
0015   software reset, clock selection, optional division and clock gating mode
0016   for peripherals.
0017
0018 properties:
0019   compatible:
0020     enum:
0021       - fsl,imx8ulp-pcc3
0022       - fsl,imx8ulp-pcc4
0023       - fsl,imx8ulp-pcc5
0024
0025   reg:
0026     maxItems: 1
0027
0028   '#clock-cells':
0029     const: 1
0030
0031   '#reset-cells':
0032     const: 1
0033
0034 required:
0035   - compatible
0036   - reg
0037   - '#clock-cells'
0038   - '#reset-cells'
0039
0040 additionalProperties: false
0041
0042 examples:
0043   # Peripheral Clock Control Module node:
0044   - |
0045     clock-controller@292d0000 {
0046         compatible = "fsl,imx8ulp-pcc3";
0047         reg = <0x292d0000 0x10000>;
0048         #clock-cells = <1>;
0049         #reset-cells = <1>;
0050     };