0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
0008
0009 maintainers:
0010 - Aisheng Dong <aisheng.dong@nxp.com>
0011
0012 description: |
0013 The Low-Power Clock Gate (LPCG) modules contain a local programming
0014 model to control the clock gates for the peripherals. An LPCG module
0015 is used to locally gate the clocks for the associated peripheral.
0016
0017 This level of clock gating is provided after the clocks are generated
0018 by the SCU resources and clock controls. Thus even if the clock is
0019 enabled by these control bits, it might still not be running based
0020 on the base resource.
0021
0022 The clock consumer should specify the desired clock by having the clock
0023 ID in its "clocks" phandle cell. See the full list of clock IDs from:
0024 include/dt-bindings/clock/imx8-lpcg.h
0025
0026 properties:
0027 compatible:
0028 oneOf:
0029 - const: fsl,imx8qxp-lpcg
0030 - items:
0031 - enum:
0032 - fsl,imx8qm-lpcg
0033 - const: fsl,imx8qxp-lpcg
0034 - enum:
0035 - fsl,imx8qxp-lpcg-adma
0036 - fsl,imx8qxp-lpcg-conn
0037 - fsl,imx8qxp-lpcg-dc
0038 - fsl,imx8qxp-lpcg-dsp
0039 - fsl,imx8qxp-lpcg-gpu
0040 - fsl,imx8qxp-lpcg-hsio
0041 - fsl,imx8qxp-lpcg-img
0042 - fsl,imx8qxp-lpcg-lsio
0043 - fsl,imx8qxp-lpcg-vpu
0044 deprecated: true
0045 reg:
0046 maxItems: 1
0047
0048 '#clock-cells':
0049 const: 1
0050
0051 clocks:
0052 description: |
0053 Input parent clocks phandle array for each clock
0054 minItems: 1
0055 maxItems: 8
0056
0057 clock-indices:
0058 description: |
0059 An integer array indicating the bit offset for each clock.
0060 Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
0061 supported LPCG clock indices.
0062 minItems: 1
0063 maxItems: 8
0064
0065 clock-output-names:
0066 description: |
0067 Shall be the corresponding names of the outputs.
0068 NOTE this property must be specified in the same order
0069 as the clock-indices property.
0070 minItems: 1
0071 maxItems: 8
0072
0073 power-domains:
0074 maxItems: 1
0075
0076 required:
0077 - compatible
0078 - reg
0079 - '#clock-cells'
0080
0081 additionalProperties: false
0082
0083 examples:
0084 - |
0085 #include <dt-bindings/clock/imx8-lpcg.h>
0086 #include <dt-bindings/firmware/imx/rsrc.h>
0087 #include <dt-bindings/interrupt-controller/arm-gic.h>
0088
0089 sdhc0_lpcg: clock-controller@5b200000 {
0090 compatible = "fsl,imx8qxp-lpcg";
0091 reg = <0x5b200000 0x10000>;
0092 #clock-cells = <1>;
0093 clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
0094 <&conn_ipg_clk>,
0095 <&conn_axi_clk>;
0096 clock-indices = <IMX_LPCG_CLK_0>,
0097 <IMX_LPCG_CLK_4>,
0098 <IMX_LPCG_CLK_5>;
0099 clock-output-names = "sdhc0_lpcg_per_clk",
0100 "sdhc0_lpcg_ipg_clk",
0101 "sdhc0_lpcg_ahb_clk";
0102 power-domains = <&pd IMX_SC_R_SDHC_0>;
0103 };
