0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
0008
0009 maintainers:
0010 - A.s. Dong <aisheng.dong@nxp.com>
0011
0012 description: |
0013 i.MX7ULP Clock functions are under joint control of the System
0014 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
0015 modules, and Core Mode Controller (CMC)1 blocks
0016
0017 The clocking scheme provides clear separation between M4 domain
0018 and A7 domain. Except for a few clock sources shared between two
0019 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
0020 and and the Fast IRC clock (FIRCLK), clock sources and clock
0021 management are separated and contained within each domain.
0022
0023 M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
0024 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
0025
0026 Note: this binding doc is only for A7 clock domain.
0027
0028 The System Clock Generation (SCG) is responsible for clock generation
0029 and distribution across this device. Functions performed by the SCG
0030 include: clock reference selection, generation of clock used to derive
0031 processor, system, peripheral bus and external memory interface clocks,
0032 source selection for peripheral clocks and control of power saving
0033 clock gating mode.
0034
0035 The clock consumer should specify the desired clock by having the clock
0036 ID in its "clocks" phandle cell.
0037 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
0038 i.MX7ULP clock IDs of each module.
0039
0040 properties:
0041 compatible:
0042 const: fsl,imx7ulp-scg1
0043
0044 reg:
0045 maxItems: 1
0046
0047 '#clock-cells':
0048 const: 1
0049
0050 clocks:
0051 items:
0052 - description: rtc osc
0053 - description: system osc
0054 - description: slow internal reference clock
0055 - description: fast internal reference clock
0056 - description: usb PLL
0057
0058 clock-names:
0059 items:
0060 - const: rosc
0061 - const: sosc
0062 - const: sirc
0063 - const: firc
0064 - const: upll
0065
0066 required:
0067 - compatible
0068 - reg
0069 - '#clock-cells'
0070 - clocks
0071 - clock-names
0072
0073 additionalProperties: false
0074
0075 examples:
0076 - |
0077 #include <dt-bindings/clock/imx7ulp-clock.h>
0078 #include <dt-bindings/interrupt-controller/arm-gic.h>
0079
0080 clock-controller@403e0000 {
0081 compatible = "fsl,imx7ulp-scg1";
0082 reg = <0x403e0000 0x10000>;
0083 clocks = <&rosc>, <&sosc>, <&sirc>,
0084 <&firc>, <&upll>;
0085 clock-names = "rosc", "sosc", "sirc",
0086 "firc", "upll";
0087 #clock-cells = <1>;
0088 };
