bindings/clock/imx7ulp-pcc-clock.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
0008
0009 maintainers:
0010   - A.s. Dong <aisheng.dong@nxp.com>
0011
0012 description: |
0013   i.MX7ULP Clock functions are under joint control of the System
0014   Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
0015   modules, and Core Mode Controller (CMC)1 blocks
0016
0017   The clocking scheme provides clear separation between M4 domain
0018   and A7 domain. Except for a few clock sources shared between two
0019   domains, such as the System Oscillator clock, the Slow IRC (SIRC),
0020   and and the Fast IRC clock (FIRCLK), clock sources and clock
0021   management are separated and contained within each domain.
0022
0023   M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
0024   A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
0025
0026   Note: this binding doc is only for A7 clock domain.
0027
0028   The Peripheral Clock Control (PCC) is responsible for clock selection,
0029   optional division and clock gating mode for peripherals in their
0030   respected power domain.
0031
0032   The clock consumer should specify the desired clock by having the clock
0033   ID in its "clocks" phandle cell.
0034   See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
0035   i.MX7ULP clock IDs of each module.
0036
0037 properties:
0038   compatible:
0039     enum:
0040       - fsl,imx7ulp-pcc2
0041       - fsl,imx7ulp-pcc3
0042
0043   reg:
0044     maxItems: 1
0045
0046   '#clock-cells':
0047     const: 1
0048
0049   clocks:
0050     items:
0051       - description: nic1 bus clock
0052       - description: nic1 clock
0053       - description: ddr clock
0054       - description: apll pfd2
0055       - description: apll pfd1
0056       - description: apll pfd0
0057       - description: usb pll
0058       - description: system osc bus clock
0059       - description: fast internal reference clock bus
0060       - description: rtc osc
0061       - description: system pll bus clock
0062
0063   clock-names:
0064     items:
0065       - const: nic1_bus_clk
0066       - const: nic1_clk
0067       - const: ddr_clk
0068       - const: apll_pfd2
0069       - const: apll_pfd1
0070       - const: apll_pfd0
0071       - const: upll
0072       - const: sosc_bus_clk
0073       - const: firc_bus_clk
0074       - const: rosc
0075       - const: spll_bus_clk
0076
0077 required:
0078   - compatible
0079   - reg
0080   - '#clock-cells'
0081   - clocks
0082   - clock-names
0083
0084 additionalProperties: false
0085
0086 examples:
0087   - |
0088     #include <dt-bindings/clock/imx7ulp-clock.h>
0089     #include <dt-bindings/interrupt-controller/arm-gic.h>
0090
0091     clock-controller@403f0000 {
0092         compatible = "fsl,imx7ulp-pcc2";
0093         reg = <0x403f0000 0x10000>;
0094         #clock-cells = <1>;
0095         clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
0096                  <&scg1 IMX7ULP_CLK_NIC1_DIV>,
0097                  <&scg1 IMX7ULP_CLK_DDR_DIV>,
0098                  <&scg1 IMX7ULP_CLK_APLL_PFD2>,
0099                  <&scg1 IMX7ULP_CLK_APLL_PFD1>,
0100                  <&scg1 IMX7ULP_CLK_APLL_PFD0>,
0101                  <&scg1 IMX7ULP_CLK_UPLL>,
0102                  <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
0103                  <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
0104                  <&scg1 IMX7ULP_CLK_ROSC>,
0105                  <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
0106          clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
0107                        "apll_pfd2", "apll_pfd1", "apll_pfd0",
0108                        "upll", "sosc_bus_clk", "firc_bus_clk",
0109                        "rosc", "spll_bus_clk";
0110     };