0001 * Hisilicon Hi3660 Clock Controller
0002
0003 The Hi3660 clock controller generates and supplies clock to various
0004 controllers within the Hi3660 SoC.
0005
0006 Required Properties:
0007
0008 - compatible: the compatible should be one of the following strings to
0009 indicate the clock controller functionality.
0010
0011 - "hisilicon,hi3660-crgctrl"
0012 - "hisilicon,hi3660-pctrl"
0013 - "hisilicon,hi3660-pmuctrl"
0014 - "hisilicon,hi3660-sctrl"
0015 - "hisilicon,hi3660-iomcu"
0016 - "hisilicon,hi3660-stub-clk"
0017
0018 - reg: physical base address of the controller and length of memory mapped
0019 region.
0020
0021 - #clock-cells: should be 1.
0022
0023 Optional Properties:
0024
0025 - mboxes: Phandle to the mailbox for sending message to MCU.
0026 (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
0027
0028 Each clock is assigned an identifier and client nodes use this identifier
0029 to specify the clock which they consume.
0030
0031 All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
0032
0033 Examples:
0034 crg_ctrl: clock-controller@fff35000 {
0035 compatible = "hisilicon,hi3660-crgctrl", "syscon";
0036 reg = <0x0 0xfff35000 0x0 0x1000>;
0037 #clock-cells = <1>;
0038 };
0039
0040 uart0: serial@fdf02000 {
0041 compatible = "arm,pl011", "arm,primecell";
0042 reg = <0x0 0xfdf02000 0x0 0x1000>;
0043 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0044 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
0045 <&crg_ctrl HI3660_PCLK>;
0046 clock-names = "uartclk", "apb_pclk";
0047 };
