0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale SAI bitclock-as-a-clock binding
0008
0009 maintainers:
0010 - Michael Walle <michael@walle.cc>
0011
0012 description: |
0013 It is possible to use the BCLK pin of a SAI module as a generic clock
0014 output. Some SoC are very constrained in their pin multiplexer
0015 configuration. Eg. pins can only be changed groups. For example, on the
0016 LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
0017 the second pins are wasted. Using this binding it is possible to use the
0018 clock of the second SAI as a MCLK clock for an audio codec, for example.
0019
0020 This is a composite of a gated clock and a divider clock.
0021
0022 properties:
0023 compatible:
0024 const: fsl,vf610-sai-clock
0025
0026 reg:
0027 maxItems: 1
0028
0029 clocks:
0030 maxItems: 1
0031
0032 '#clock-cells':
0033 const: 0
0034
0035 required:
0036 - compatible
0037 - reg
0038 - clocks
0039 - '#clock-cells'
0040
0041 additionalProperties: false
0042
0043 examples:
0044 - |
0045 soc {
0046 #address-cells = <2>;
0047 #size-cells = <2>;
0048
0049 mclk: clock-mclk@f130080 {
0050 compatible = "fsl,vf610-sai-clock";
0051 reg = <0x0 0xf130080 0x0 0x80>;
0052 #clock-cells = <0>;
0053 clocks = <&parentclk>;
0054 };
0055 };
