0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
0008
0009 maintainers:
0010 - Wen He <wen.he_1@nxp.com>
0011
0012 description: |
0013 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
0014 interface in the display core, as implemented in TSMC CLN28HPM PLL.
0015 which generate and offers pixel clocks to Display.
0016
0017 properties:
0018 compatible:
0019 const: fsl,ls1028a-plldig
0020
0021 reg:
0022 maxItems: 1
0023
0024 clocks:
0025 maxItems: 1
0026
0027 '#clock-cells':
0028 const: 0
0029
0030 fsl,vco-hz:
0031 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
0032 of this PLL cannot be changed during runtime only at startup. Therefore,
0033 the output frequencies are very limited and might not even closely match
0034 the requested frequency. To work around this restriction the user may specify
0035 its own desired VCO frequency for the PLL.
0036 minimum: 650000000
0037 maximum: 1300000000
0038 default: 1188000000
0039
0040 required:
0041 - compatible
0042 - reg
0043 - clocks
0044 - '#clock-cells'
0045
0046 additionalProperties: false
0047
0048 examples:
0049 # Display PIXEL Clock node:
0050 - |
0051 dpclk: clock-display@f1f0000 {
0052 compatible = "fsl,ls1028a-plldig";
0053 reg = <0xf1f0000 0xffff>;
0054 #clock-cells = <0>;
0055 clocks = <&osc_27m>;
0056 };
0057
0058 ...
