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OSCL-LXR

 
 

    


0001 PLL divider based Dove clocks
0002 
0003 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
0004 high speed clocks for a number of peripherals.  These dividers are part of
0005 the PMU, and thus this node should be a child of the PMU node.
0006 
0007 The following clocks are provided:
0008 
0009 ID      Clock
0010 -------------
0011 0       AXI bus clock
0012 1       GPU clock
0013 2       VMeta clock
0014 3       LCD clock
0015 
0016 Required properties:
0017 - compatible : shall be "marvell,dove-divider-clock"
0018 - reg : shall be the register address of the Core PLL and Clock Divider
0019    Control 0 register.  This will cover that register, as well as the
0020    Core PLL and Clock Divider Control 1 register.  Thus, it will have
0021    a size of 8.
0022 - #clock-cells : from common clock binding; shall be set to 1
0023 
0024 divider_clk: core-clock@64 {
0025         compatible = "marvell,dove-divider-clock";
0026         reg = <0x0064 0x8>;
0027         #clock-cells = <1>;
0028 };