0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/calxeda.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Device Tree Clock bindings for Calxeda highbank platform
0008
0009 description: |
0010 This binding covers the Calxeda SoC internal peripheral and bus clocks
0011 as used by peripherals. The clocks live inside the "system register"
0012 region of the SoC, so are typically presented as children of an
0013 "hb-sregs" node.
0014
0015 maintainers:
0016 - Andre Przywara <andre.przywara@arm.com>
0017
0018 properties:
0019 "#clock-cells":
0020 const: 0
0021
0022 compatible:
0023 enum:
0024 - calxeda,hb-pll-clock
0025 - calxeda,hb-a9periph-clock
0026 - calxeda,hb-a9bus-clock
0027 - calxeda,hb-emmc-clock
0028
0029 reg:
0030 maxItems: 1
0031
0032 clocks:
0033 maxItems: 1
0034
0035 required:
0036 - "#clock-cells"
0037 - compatible
0038 - clocks
0039 - reg
0040
0041 additionalProperties: false
0042
0043 examples:
0044 - |
0045 sregs@3fffc000 {
0046 compatible = "calxeda,hb-sregs";
0047 reg = <0x3fffc000 0x1000>;
0048
0049 clocks {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 osc: oscillator {
0054 #clock-cells = <0>;
0055 compatible = "fixed-clock";
0056 clock-frequency = <33333000>;
0057 };
0058
0059 ddrpll: ddrpll@108 {
0060 #clock-cells = <0>;
0061 compatible = "calxeda,hb-pll-clock";
0062 clocks = <&osc>;
0063 reg = <0x108>;
0064 };
0065
0066 a9pll: a9pll@100 {
0067 #clock-cells = <0>;
0068 compatible = "calxeda,hb-pll-clock";
0069 clocks = <&osc>;
0070 reg = <0x100>;
0071 };
0072
0073 a9periphclk: a9periphclk@104 {
0074 #clock-cells = <0>;
0075 compatible = "calxeda,hb-a9periph-clock";
0076 clocks = <&a9pll>;
0077 reg = <0x104>;
0078 };
0079 };
0080 };
0081
0082 ...
