0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Broadcom iProc Family Clocks
0008
0009 maintainers:
0010 - Ray Jui <rjui@broadcom.com>
0011 - Scott Branden <sbranden@broadcom.com>
0012
0013 description: |
0014 The iProc clock controller manages clocks that are common to the iProc family.
0015 An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
0016 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
0017 comprises of several leaf clocks
0018
0019 ASIU clocks are a special case. These clocks are derived directly from the
0020 reference clock of the onboard crystal.
0021
0022 properties:
0023 compatible:
0024 enum:
0025 - brcm,bcm63138-armpll
0026 - brcm,cygnus-armpll
0027 - brcm,cygnus-genpll
0028 - brcm,cygnus-lcpll0
0029 - brcm,cygnus-mipipll
0030 - brcm,cygnus-asiu-clk
0031 - brcm,cygnus-audiopll
0032 - brcm,hr2-armpll
0033 - brcm,nsp-armpll
0034 - brcm,nsp-genpll
0035 - brcm,nsp-lcpll0
0036 - brcm,ns2-genpll-scr
0037 - brcm,ns2-genpll-sw
0038 - brcm,ns2-lcpll-ddr
0039 - brcm,ns2-lcpll-ports
0040 - brcm,sr-genpll0
0041 - brcm,sr-genpll1
0042 - brcm,sr-genpll2
0043 - brcm,sr-genpll3
0044 - brcm,sr-genpll4
0045 - brcm,sr-genpll5
0046 - brcm,sr-genpll6
0047 - brcm,sr-lcpll0
0048 - brcm,sr-lcpll1
0049 - brcm,sr-lcpll-pcie
0050
0051 reg:
0052 minItems: 1
0053 items:
0054 - description: base register
0055 - description: power register
0056 - description: ASIU or split status register
0057
0058 clocks:
0059 description: The input parent clock phandle for the PLL / ASIU clock. For
0060 most iProc PLLs, this is an onboard crystal with a fixed rate.
0061 maxItems: 1
0062
0063 '#clock-cells':
0064 true
0065
0066 clock-output-names:
0067 minItems: 1
0068 maxItems: 45
0069
0070 allOf:
0071 - if:
0072 properties:
0073 compatible:
0074 contains:
0075 enum:
0076 - brcm,cygnus-armpll
0077 - brcm,nsp-armpll
0078 then:
0079 properties:
0080 '#clock-cells':
0081 const: 0
0082 else:
0083 properties:
0084 '#clock-cells':
0085 const: 1
0086 required:
0087 - clock-output-names
0088 - if:
0089 properties:
0090 compatible:
0091 contains:
0092 enum:
0093 - brcm,cygnus-armpll
0094 - brcm,cygnus-genpll
0095 - brcm,cygnus-lcpll0
0096 - brcm,cygnus-mipipll
0097 - brcm,cygnus-asiu-clk
0098 - brcm,cygnus-audiopll
0099 then:
0100 properties:
0101 clock-output-names:
0102 description: |
0103 The following table defines the set of PLL/clock index and ID for Cygnus.
0104 These clock IDs are defined in:
0105 "include/dt-bindings/clock/bcm-cygnus.h"
0106
0107 Clock Source (Parent) Index ID
0108 ----- --------------- ----- --
0109 crystal N/A N/A N/A
0110
0111 armpll crystal N/A N/A
0112
0113 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
0114 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
0115 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
0116
0117 genpll crystal 0 BCM_CYGNUS_GENPLL
0118 axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
0119 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
0120 ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
0121 enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
0122 audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
0123 can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
0124
0125 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
0126 pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
0127 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
0128 sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
0129 usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
0130 smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
0131 ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
0132
0133 mipipll crystal 0 BCM_CYGNUS_MIPIPLL
0134 ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
0135 ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
0136 ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
0137 ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
0138 ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
0139 ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
0140
0141 audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
0142 ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
0143 ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
0144 ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
0145 - if:
0146 properties:
0147 compatible:
0148 contains:
0149 enum:
0150 - brcm,hr2-armpll
0151 then:
0152 properties:
0153 clock-output-names:
0154 description: |
0155 The following table defines the set of PLL/clock for Hurricane 2:
0156
0157 Clock Source Index ID
0158 ----- ------ ----- --
0159 crystal N/A N/A N/A
0160
0161 armpll crystal N/A N/A
0162 - if:
0163 properties:
0164 compatible:
0165 contains:
0166 enum:
0167 - brcm,nsp-armpll
0168 - brcm,nsp-genpll
0169 - brcm,nsp-lcpll0
0170 then:
0171 properties:
0172 clock-output-names:
0173 description: |
0174 The following table defines the set of PLL/clock index and ID for Northstar and
0175 Northstar Plus. These clock IDs are defined in:
0176 "include/dt-bindings/clock/bcm-nsp.h"
0177
0178 Clock Source Index ID
0179 ----- ------ ----- --
0180 crystal N/A N/A N/A
0181
0182 armpll crystal N/A N/A
0183
0184 genpll crystal 0 BCM_NSP_GENPLL
0185 phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
0186 ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
0187 usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
0188 iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
0189 sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
0190 sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
0191
0192 lcpll0 crystal 0 BCM_NSP_LCPLL0
0193 pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
0194 sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
0195 ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
0196 - if:
0197 properties:
0198 compatible:
0199 contains:
0200 enum:
0201 - brcm,ns2-genpll-scr
0202 - brcm,ns2-genpll-sw
0203 - brcm,ns2-lcpll-ddr
0204 - brcm,ns2-lcpll-ports
0205 then:
0206 properties:
0207 clock-output-names:
0208 description: |
0209 The following table defines the set of PLL/clock index and ID for Northstar 2.
0210 These clock IDs are defined in:
0211 "include/dt-bindings/clock/bcm-ns2.h"
0212
0213 Clock Source Index ID
0214 ----- ------ ----- --
0215 crystal N/A N/A N/A
0216
0217 genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
0218 scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
0219 fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
0220 audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
0221 ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
0222 ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
0223 ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
0224
0225 genpll_sw crystal 0 BCM_NS2_GENPLL_SW
0226 rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
0227 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
0228 nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
0229 chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
0230 port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
0231 sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
0232
0233 lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
0234 pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
0235 ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
0236 ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
0237 ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
0238 ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
0239 ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
0240
0241 lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
0242 wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
0243 rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
0244 ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
0245 ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
0246 ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
0247 ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
0248 - if:
0249 properties:
0250 compatible:
0251 contains:
0252 enum:
0253 - brcm,sr-genpll0
0254 - brcm,sr-genpll1
0255 - brcm,sr-genpll2
0256 - brcm,sr-genpll3
0257 - brcm,sr-genpll4
0258 - brcm,sr-genpll5
0259 - brcm,sr-genpll6
0260 - brcm,sr-lcpll0
0261 - brcm,sr-lcpll1
0262 - brcm,sr-lcpll-pcie
0263 then:
0264 properties:
0265 clock-output-names:
0266 description: |
0267 The following table defines the set of PLL/clock index and ID for Stingray.
0268 These clock IDs are defined in:
0269 "include/dt-bindings/clock/bcm-sr.h"
0270
0271 Clock Source Index ID
0272 ----- ------ ----- --
0273 crystal N/A N/A N/A
0274 crmu_ref25m crystal N/A N/A
0275
0276 genpll0 crystal 0 BCM_SR_GENPLL0
0277 clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
0278 clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
0279 clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
0280 clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
0281 clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
0282 clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
0283
0284 genpll1 crystal 0 BCM_SR_GENPLL1
0285 clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
0286 clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
0287
0288 genpll2 crystal 0 BCM_SR_GENPLL2
0289 clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
0290 clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
0291 clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
0292 clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
0293 clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
0294 clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
0295
0296 genpll3 crystal 0 BCM_SR_GENPLL3
0297 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
0298 clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
0299
0300 genpll4 crystal 0 BCM_SR_GENPLL4
0301 clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
0302 clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
0303 clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
0304 clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
0305 clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
0306
0307 genpll5 crystal 0 BCM_SR_GENPLL5
0308 clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
0309 clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
0310 clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
0311
0312 genpll6 crystal 0 BCM_SR_GENPLL6
0313 clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
0314
0315 lcpll0 crystal 0 BCM_SR_LCPLL0
0316 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
0317 clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
0318 clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
0319 clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
0320
0321 lcpll1 crystal 0 BCM_SR_LCPLL1
0322 clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
0323 clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
0324 clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
0325
0326 lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
0327 clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
0328 - if:
0329 properties:
0330 compatible:
0331 contains:
0332 const: brcm,cygnus-genpll
0333 then:
0334 properties:
0335 clock-output-names:
0336 items:
0337 - const: genpll
0338 - const: axi21
0339 - const: 250mhz
0340 - const: ihost_sys
0341 - const: enet_sw
0342 - const: audio_125
0343 - const: can
0344 - if:
0345 properties:
0346 compatible:
0347 contains:
0348 const: brcm,nsp-lcpll0
0349 then:
0350 properties:
0351 clock-output-names:
0352 items:
0353 - const: lcpll0
0354 - const: pcie_phy
0355 - const: sdio
0356 - const: ddr_phy
0357 - if:
0358 properties:
0359 compatible:
0360 contains:
0361 const: brcm,nsp-genpll
0362 then:
0363 properties:
0364 clock-output-names:
0365 items:
0366 - const: genpll
0367 - const: phy
0368 - const: ethernetclk
0369 - const: usbclk
0370 - const: iprocfast
0371 - const: sata1
0372 - const: sata2
0373
0374 required:
0375 - reg
0376 - clocks
0377 - '#clock-cells'
0378
0379 additionalProperties: false
0380
0381 examples:
0382 - |
0383 osc1: oscillator {
0384 #clock-cells = <0>;
0385 compatible = "fixed-clock";
0386 clock-frequency = <25000000>;
0387 };
0388
0389 genpll@301d000 {
0390 #clock-cells = <1>;
0391 compatible = "brcm,cygnus-genpll";
0392 reg = <0x301d000 0x2c>, <0x301c020 0x4>;
0393 clocks = <&os1c>;
0394 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
0395 "enet_sw", "audio_125", "can";
0396 };
0397 - |
0398 osc2: oscillator {
0399 #clock-cells = <0>;
0400 compatible = "fixed-clock";
0401 clock-frequency = <25000000>;
0402 };
0403
0404 asiu_clks@301d048 {
0405 #clock-cells = <1>;
0406 compatible = "brcm,cygnus-asiu-clk";
0407 reg = <0x301d048 0xc>, <0x180aa024 0x4>;
0408 clocks = <&osc2>;
0409 clock-output-names = "keypad", "adc/touch", "pwm";
0410 };
0411 - |
0412 arm_clk@0 {
0413 #clock-cells = <0>;
0414 compatible = "brcm,nsp-armpll";
0415 clocks = <&osc>;
0416 reg = <0x0 0x1000>;
0417 };
