0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Baikal-T1 Clock Control Unit PLL
0009
0010 maintainers:
0011 - Serge Semin <fancer.lancer@gmail.com>
0012
0013 description: |
0014 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
0015 responsible for the chip subsystems clocking and resetting. The CCU is
0016 connected with an external fixed rate oscillator, which signal is transformed
0017 into clocks of various frequencies and then propagated to either individual
0018 IP-blocks or to groups of blocks (clock domains). The transformation is done
0019 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
0020 It's logically divided into the next components:
0021 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
0022 in general can provide any frequency supported by the CCU PLLs).
0023 2) PLLs clocks generators (PLLs) - described in this binding file.
0024 3) AXI-bus clock dividers (AXI).
0025 4) System devices reference clock dividers (SYS).
0026 which are connected with each other as shown on the next figure:
0027
0028 +---------------+
0029 | Baikal-T1 CCU |
0030 | +----+------|- MIPS P5600 cores
0031 | +-|PLLs|------|- DDR controller
0032 | | +----+ |
0033 +----+ | | | | |
0034 |XTAL|--|-+ | | +---+-|
0035 +----+ | | | +-|AXI|-|- AXI-bus
0036 | | | +---+-|
0037 | | | |
0038 | | +----+---+-|- APB-bus
0039 | +-------|SYS|-|- Low-speed Devices
0040 | +---+-|- High-speed Devices
0041 +---------------+
0042
0043 Each CCU sub-block is represented as a separate dts-node and has an
0044 individual driver to be bound with.
0045
0046 In order to create signals of wide range frequencies the external oscillator
0047 output is primarily connected to a set of CCU PLLs. There are five PLLs
0048 to create a clock for the MIPS P5600 cores, the embedded DDR controller,
0049 SATA, Ethernet and PCIe domains. The last three domains though named by the
0050 biggest system interfaces in fact include nearly all of the rest SoC
0051 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
0052 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
0053 the PLL configuration procedure. The PLLs work as depicted on the next
0054 diagram:
0055
0056 +--------------------------+
0057 | |
0058 +-->+---+ +---+ +---+ | +---+ 0|\
0059 CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
0060 +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
0061 CLKOD---------C----------------+ 1| |
0062 +--------C--------------------------->|/
0063 | | ^
0064 Rclk-+->+---+ | |
0065 CLKR--->|/NR|-+ |
0066 +---+ |
0067 BYPASS--------------------------------------+
0068 BWADJ--->
0069
0070 where Rclk is the reference clock coming from XTAL, NR - reference clock
0071 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
0072 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
0073 the binding supports the PLL dividers configuration in accordance with a
0074 requested rate, while bypassing and bandwidth adjustment settings can be
0075 added in future if it gets to be necessary.
0076
0077 The PLLs CLKOUT is then either directly connected with the corresponding
0078 clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
0079 divider to create a signal required for the clock domain.
0080
0081 The CCU PLL dts-node uses the common clock bindings with no custom
0082 parameters. The list of exported clocks can be found in
0083 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
0084 Baikal-T1 SoC System Controller its DT node is supposed to be a child of
0085 later one.
0086
0087 properties:
0088 compatible:
0089 const: baikal,bt1-ccu-pll
0090
0091 reg:
0092 maxItems: 1
0093
0094 "#clock-cells":
0095 const: 1
0096
0097 clocks:
0098 description: External reference clock
0099 maxItems: 1
0100
0101 clock-names:
0102 const: ref_clk
0103
0104 additionalProperties: false
0105
0106 required:
0107 - compatible
0108 - "#clock-cells"
0109 - clocks
0110 - clock-names
0111
0112 examples:
0113 # Clock Control Unit PLL node:
0114 - |
0115 clock-controller@1f04d000 {
0116 compatible = "baikal,bt1-ccu-pll";
0117 reg = <0x1f04d000 0x028>;
0118 #clock-cells = <1>;
0119
0120 clocks = <&clk25m>;
0121 clock-names = "ref_clk";
0122 };
0123 # Required external oscillator:
0124 - |
0125 clk25m: clock-oscillator-25m {
0126 compatible = "fixed-clock";
0127 #clock-cells = <0>;
0128 clock-frequency = <25000000>;
0129 clock-output-names = "clk25m";
0130 };
0131 ...
