0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Baikal-T1 Clock Control Unit Dividers
0009
0010 maintainers:
0011 - Serge Semin <fancer.lancer@gmail.com>
0012
0013 description: |
0014 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
0015 responsible for the chip subsystems clocking and resetting. The CCU is
0016 connected with an external fixed rate oscillator, which signal is transformed
0017 into clocks of various frequencies and then propagated to either individual
0018 IP-blocks or to groups of blocks (clock domains). The transformation is done
0019 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
0020 later ones are described in this binding. Each clock domain can be also
0021 individually reset by using the domain clocks divider configuration
0022 registers. Baikal-T1 CCU is logically divided into the next components:
0023 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
0024 in general can provide any frequency supported by the CCU PLLs).
0025 2) PLLs clocks generators (PLLs).
0026 3) AXI-bus clock dividers (AXI) - described in this binding file.
0027 4) System devices reference clock dividers (SYS) - described in this binding
0028 file.
0029 which are connected with each other as shown on the next figure:
0030
0031 +---------------+
0032 | Baikal-T1 CCU |
0033 | +----+------|- MIPS P5600 cores
0034 | +-|PLLs|------|- DDR controller
0035 | | +----+ |
0036 +----+ | | | | |
0037 |XTAL|--|-+ | | +---+-|
0038 +----+ | | | +-|AXI|-|- AXI-bus
0039 | | | +---+-|
0040 | | | |
0041 | | +----+---+-|- APB-bus
0042 | +-------|SYS|-|- Low-speed Devices
0043 | +---+-|- High-speed Devices
0044 +---------------+
0045
0046 Each sub-block is represented as a separate DT node and has an individual
0047 driver to be bound with.
0048
0049 In order to create signals of wide range frequencies the external oscillator
0050 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
0051 then passed over CCU dividers to create signals required for the target clock
0052 domain (like AXI-bus or System Device consumers). The dividers have the
0053 following structure:
0054
0055 +--------------+
0056 CLKIN --|->+----+ 1|\ |
0057 SETCLK--|--|/DIV|->| | |
0058 CLKDIV--|--| | | |-|->CLKLOUT
0059 LOCK----|--+----+ | | |
0060 | |/ |
0061 | | |
0062 EN------|-----------+ |
0063 RST-----|--------------|->RSTOUT
0064 +--------------+
0065
0066 where CLKIN is the reference clock coming either from CCU PLLs or from an
0067 external clock oscillator, SETCLK - a command to update the output clock in
0068 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
0069 the output clock stabilization, EN - enable/disable the divider block,
0070 RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
0071 peculiarities the dividers may lack of some functionality depicted on the
0072 figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
0073 clock provider just doesn't expose either switching functions, or the rate
0074 configuration, or both of them.
0075
0076 The clock dividers, which output clock is then consumed by the SoC individual
0077 devices, are united into a single clocks provider called System Devices CCU.
0078 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
0079 are called AXI-bus CCU. Both of them use the common clock bindings with no
0080 custom properties. The list of exported clocks and reset signals can be found
0081 in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
0082 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
0083 are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
0084 to be a children of later one.
0085
0086 if:
0087 properties:
0088 compatible:
0089 contains:
0090 const: baikal,bt1-ccu-axi
0091
0092 then:
0093 properties:
0094 clocks:
0095 items:
0096 - description: CCU SATA PLL output clock
0097 - description: CCU PCIe PLL output clock
0098 - description: CCU Ethernet PLL output clock
0099
0100 clock-names:
0101 items:
0102 - const: sata_clk
0103 - const: pcie_clk
0104 - const: eth_clk
0105
0106 else:
0107 properties:
0108 clocks:
0109 items:
0110 - description: External reference clock
0111 - description: CCU SATA PLL output clock
0112 - description: CCU PCIe PLL output clock
0113 - description: CCU Ethernet PLL output clock
0114
0115 clock-names:
0116 items:
0117 - const: ref_clk
0118 - const: sata_clk
0119 - const: pcie_clk
0120 - const: eth_clk
0121
0122 properties:
0123 compatible:
0124 enum:
0125 - baikal,bt1-ccu-axi
0126 - baikal,bt1-ccu-sys
0127
0128 reg:
0129 maxItems: 1
0130
0131 "#clock-cells":
0132 const: 1
0133
0134 "#reset-cells":
0135 const: 1
0136
0137 clocks: true
0138
0139 clock-names: true
0140
0141 additionalProperties: false
0142
0143 required:
0144 - compatible
0145 - "#clock-cells"
0146 - clocks
0147 - clock-names
0148
0149 examples:
0150 # AXI-bus Clock Control Unit node:
0151 - |
0152 #include <dt-bindings/clock/bt1-ccu.h>
0153
0154 clock-controller@1f04d030 {
0155 compatible = "baikal,bt1-ccu-axi";
0156 reg = <0x1f04d030 0x030>;
0157 #clock-cells = <1>;
0158 #reset-cells = <1>;
0159
0160 clocks = <&ccu_pll CCU_SATA_PLL>,
0161 <&ccu_pll CCU_PCIE_PLL>,
0162 <&ccu_pll CCU_ETH_PLL>;
0163 clock-names = "sata_clk", "pcie_clk", "eth_clk";
0164 };
0165 # System Devices Clock Control Unit node:
0166 - |
0167 #include <dt-bindings/clock/bt1-ccu.h>
0168
0169 clock-controller@1f04d060 {
0170 compatible = "baikal,bt1-ccu-sys";
0171 reg = <0x1f04d060 0x0a0>;
0172 #clock-cells = <1>;
0173 #reset-cells = <1>;
0174
0175 clocks = <&clk25m>,
0176 <&ccu_pll CCU_SATA_PLL>,
0177 <&ccu_pll CCU_PCIE_PLL>,
0178 <&ccu_pll CCU_ETH_PLL>;
0179 clock-names = "ref_clk", "sata_clk", "pcie_clk",
0180 "eth_clk";
0181 };
0182 # Required Clock Control Unit PLL node:
0183 - |
0184 ccu_pll: clock-controller@1f04d000 {
0185 compatible = "baikal,bt1-ccu-pll";
0186 reg = <0x1f04d000 0x028>;
0187 #clock-cells = <1>;
0188
0189 clocks = <&clk25m>;
0190 clock-names = "ref_clk";
0191 };
0192 ...
