0001 * Peripheral Clock bindings for Marvell Armada 37xx SoCs
0002
0003 Marvell Armada 37xx SoCs provide peripheral clocks which are
0004 used as clock source for the peripheral of the SoC.
0005
0006 There are two different blocks associated to north bridge and south
0007 bridge.
0008
0009 The peripheral clock consumer should specify the desired clock by
0010 having the clock ID in its "clocks" phandle cell.
0011
0012 The following is a list of provided IDs for Armada 3700 North bridge clocks:
0013 ID Clock name Description
0014 -----------------------------------
0015 0 mmc MMC controller
0016 1 sata_host Sata Host
0017 2 sec_at Security AT
0018 3 sac_dap Security DAP
0019 4 tsecm Security Engine
0020 5 setm_tmx Serial Embedded Trace Module
0021 6 avs Adaptive Voltage Scaling
0022 7 sqf SPI
0023 8 pwm PWM
0024 9 i2c_2 I2C 2
0025 10 i2c_1 I2C 1
0026 11 ddr_phy DDR PHY
0027 12 ddr_fclk DDR F clock
0028 13 trace Trace
0029 14 counter Counter
0030 15 eip97 EIP 97
0031 16 cpu CPU
0032
0033 The following is a list of provided IDs for Armada 3700 South bridge clocks:
0034 ID Clock name Description
0035 -----------------------------------
0036 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
0037 1 gbe-core parent clock for Gigabit Ethernet core
0038 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
0039 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
0040 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
0041 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
0042 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
0043 7 gbe1-core Gigabit Ethernet core port 1
0044 8 gbe0-core Gigabit Ethernet core port 0
0045 9 gbe-bm Gigabit Ethernet Buffer Manager
0046 10 sdio SDIO
0047 11 usb32-sub2-sys USB 2 clock
0048 12 usb32-ss-sys USB 3 clock
0049 13 pcie PCIe controller
0050
0051 Required properties:
0052
0053 - compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
0054 north bridge block, or
0055 "marvell,armada-3700-periph-clock-sb" for the south bridge block
0056 - reg : must be the register address of North/South Bridge Clock register
0057 - #clock-cells : from common clock binding; shall be set to 1
0058
0059 - clocks : list of the parent clock phandle in the following order:
0060 TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
0061
0062
0063 Example:
0064
0065 nb_perih_clk: nb-periph-clk@13000{
0066 compatible = "marvell,armada-3700-periph-clock-nb";
0067 reg = <0x13000 0x1000>;
0068 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
0069 <&tbg 3>, <&xtalclk>;
0070 #clock-cells = <1>;
0071 };
