0001 Device Tree Clock bindings for Altera's SoCFPGA platform
0002
0003 This binding uses the common clock binding[1].
0004
0005 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0006
0007 Required properties:
0008 - compatible : shall be one of the following:
0009 "altr,socfpga-pll-clock" - for a PLL clock
0010 "altr,socfpga-perip-clock" - The peripheral clock divided from the
0011 PLL clock.
0012 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
0013 can get gated.
0014
0015 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
0016 - clocks : shall be the input parent clock phandle for the clock. This is
0017 either an oscillator or a pll output.
0018 - #clock-cells : from common clock binding, shall be set to 0.
0019
0020 Optional properties:
0021 - fixed-divider : If clocks have a fixed divider value, use this property.
0022 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
0023 and the bit index.
0024 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
0025 the divider register, bit shift, and width.
0026 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
0027 the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
0028 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
0029 hold/delay times that is needed for the SD/MMC CIU clock. The values of both
0030 can be 0-315 degrees, in 45 degree increments.
