0001 # SPDX-License-Identifier: GPL-2.0+
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 properties:
0014 "#clock-cells":
0015 const: 1
0016
0017 "#reset-cells":
0018 const: 1
0019
0020 compatible:
0021 const: allwinner,sun9i-a80-de-clks
0022
0023 reg:
0024 maxItems: 1
0025
0026 clocks:
0027 items:
0028 - description: Bus Clock
0029 - description: RAM Bus Clock
0030 - description: Module Clock
0031
0032 clock-names:
0033 items:
0034 - const: mod
0035 - const: dram
0036 - const: bus
0037
0038 resets:
0039 maxItems: 1
0040
0041 required:
0042 - "#clock-cells"
0043 - "#reset-cells"
0044 - compatible
0045 - reg
0046 - clocks
0047 - clock-names
0048 - resets
0049
0050 additionalProperties: false
0051
0052 examples:
0053 - |
0054 #include <dt-bindings/clock/sun9i-a80-ccu.h>
0055 #include <dt-bindings/reset/sun9i-a80-ccu.h>
0056
0057 de_clocks: clock@3000000 {
0058 compatible = "allwinner,sun9i-a80-de-clks";
0059 reg = <0x03000000 0x30>;
0060 clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
0061 clock-names = "mod", "dram", "bus";
0062 resets = <&ccu RST_BUS_DE>;
0063 #clock-cells = <1>;
0064 #reset-cells = <1>;
0065 };
0066
0067 ...
