0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 deprecated: true
0014
0015 properties:
0016 "#clock-cells":
0017 const: 0
0018
0019 "#reset-cells":
0020 const: 1
0021
0022 compatible:
0023 enum:
0024 - allwinner,sun4i-a10-tcon-ch0-clk
0025 - allwinner,sun4i-a10-tcon-ch1-clk
0026
0027 reg:
0028 maxItems: 1
0029
0030 clocks:
0031 maxItems: 4
0032 description: >
0033 The parent order must match the hardware programming order.
0034
0035 clock-output-names:
0036 maxItems: 1
0037
0038 required:
0039 - "#clock-cells"
0040 - compatible
0041 - reg
0042 - clocks
0043 - clock-output-names
0044
0045 if:
0046 properties:
0047 compatible:
0048 contains:
0049 const: allwinner,sun4i-a10-tcon-ch0-clk
0050
0051 then:
0052 required:
0053 - "#reset-cells"
0054
0055 additionalProperties: false
0056
0057 examples:
0058 - |
0059 clk@1c20118 {
0060 #clock-cells = <0>;
0061 #reset-cells = <1>;
0062 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
0063 reg = <0x01c20118 0x4>;
0064 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
0065 clock-output-names = "tcon-ch0-sclk";
0066 };
0067
0068 - |
0069 clk@1c2012c {
0070 #clock-cells = <0>;
0071 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
0072 reg = <0x01c2012c 0x4>;
0073 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
0074 clock-output-names = "tcon-ch1-sclk";
0075 };
0076
0077 ...
