0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner A10 Peripheral PLL Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 deprecated: true
0014
0015 properties:
0016 "#clock-cells":
0017 const: 1
0018 description: >
0019 The first output is the SATA clock output, the second is the
0020 regular PLL output, the third is a PLL output at twice the rate.
0021
0022 compatible:
0023 const: allwinner,sun4i-a10-pll6-clk
0024
0025 reg:
0026 maxItems: 1
0027
0028 clocks:
0029 maxItems: 1
0030
0031 clock-output-names:
0032 maxItems: 3
0033
0034 required:
0035 - "#clock-cells"
0036 - compatible
0037 - reg
0038 - clocks
0039 - clock-output-names
0040
0041 additionalProperties: false
0042
0043 examples:
0044 - |
0045 clk@1c20028 {
0046 #clock-cells = <1>;
0047 compatible = "allwinner,sun4i-a10-pll6-clk";
0048 reg = <0x01c20028 0x4>;
0049 clocks = <&osc24M>;
0050 clock-output-names = "pll6_sata", "pll6_other", "pll6";
0051 };
0052
0053 ...
