0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Binding for Analog Devices AXI clkgen pcore clock generator
0008
0009 maintainers:
0010 - Lars-Peter Clausen <lars@metafoo.de>
0011 - Michael Hennerich <michael.hennerich@analog.com>
0012
0013 description: |
0014 The axi_clkgen IP core is a software programmable clock generator,
0015 that can be synthesized on various FPGA platforms.
0016
0017 Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - adi,axi-clkgen-2.00.a
0023 - adi,zynqmp-axi-clkgen-2.00.a
0024
0025 clocks:
0026 description:
0027 Specifies the reference clock(s) from which the output frequency is
0028 derived. This must either reference one clock if only the first clock
0029 input is connected or two if both clock inputs are connected.
0030 minItems: 1
0031 maxItems: 2
0032
0033 '#clock-cells':
0034 const: 0
0035
0036 reg:
0037 maxItems: 1
0038
0039 required:
0040 - compatible
0041 - reg
0042 - clocks
0043 - '#clock-cells'
0044
0045 additionalProperties: false
0046
0047 examples:
0048 - |
0049 clock-controller@ff000000 {
0050 compatible = "adi,axi-clkgen-2.00.a";
0051 #clock-cells = <0>;
0052 reg = <0xff000000 0x1000>;
0053 clocks = <&osc 1>;
0054 };
