0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Texas Instruments interconnect target module binding
0008
0009 maintainers:
0010 - Tony Lindgren <tony@atomide.com>
0011
0012 description:
0013 Texas Instruments SoCs can have a generic interconnect target module
0014 for devices connected to various interconnects such as L3 interconnect
0015 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
0016 is mostly used for interaction between module and Power, Reset and Clock
0017 Manager PRCM. It participates in the OCP Disconnect Protocol, but other
0018 than that it is mostly independent of the interconnect.
0019
0020 Each interconnect target module can have one or more devices connected to
0021 it. There is a set of control registers for managing the interconnect target
0022 module clocks, idle modes and interconnect level resets.
0023
0024 The interconnect target module control registers are sprinkled into the
0025 unused register address space of the first child device IP block managed by
0026 the interconnect target module. Typically the register names are REVISION,
0027 SYSCONFIG and SYSSTATUS.
0028
0029 properties:
0030 $nodename:
0031 pattern: "^target-module(@[0-9a-f]+)?$"
0032
0033 compatible:
0034 oneOf:
0035 - items:
0036 - enum:
0037 - ti,sysc-omap2
0038 - ti,sysc-omap4
0039 - ti,sysc-omap4-simple
0040 - ti,sysc-omap2-timer
0041 - ti,sysc-omap4-timer
0042 - ti,sysc-omap3430-sr
0043 - ti,sysc-omap3630-sr
0044 - ti,sysc-omap4-sr
0045 - ti,sysc-omap3-sham
0046 - ti,sysc-omap-aes
0047 - ti,sysc-mcasp
0048 - ti,sysc-dra7-mcasp
0049 - ti,sysc-usb-host-fs
0050 - ti,sysc-dra7-mcan
0051 - ti,sysc-pruss
0052 - const: ti,sysc
0053 - items:
0054 - const: ti,sysc
0055
0056 reg:
0057 description:
0058 Interconnect target module control registers consisting of
0059 REVISION, SYSCONFIG and SYSSTATUS registers as defined in the
0060 Technical Reference Manual for the SoC.
0061 minItems: 1
0062 maxItems: 3
0063
0064 reg-names:
0065 description:
0066 Interconnect target module control register names consisting
0067 of "rev", "sysc" and "syss".
0068 oneOf:
0069 - minItems: 1
0070 items:
0071 - const: rev
0072 - const: sysc
0073 - const: syss
0074 - items:
0075 - const: rev
0076 - const: syss
0077 - enum: [ sysc, syss ]
0078
0079 power-domains:
0080 description: Target module power domain if available.
0081 maxItems: 1
0082
0083 clocks:
0084 description:
0085 Target module clocks consisting of one functional clock, one
0086 interface clock, and up to 8 module specific optional clocks.
0087 Some modules may have only the functional clock, and some have
0088 no configurable clocks.
0089 minItems: 1
0090 maxItems: 4
0091
0092 clock-names:
0093 description:
0094 Target module clock names like "fck", "ick", "optck1", "optck2"
0095 if the clocks are configurable.
0096 oneOf:
0097 - enum: [ ick, fck, sys_clk ]
0098 - items:
0099 - const: fck
0100 - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
0101 - items:
0102 - const: fck
0103 - const: phy-clk
0104 - const: phy-clk-div
0105 - items:
0106 - const: fck
0107 - const: hdmi_clk
0108 - const: sys_clk
0109 - const: tv_clk
0110 - items:
0111 - const: fck
0112 - const: ahclkx
0113 - const: ahclkr
0114
0115 resets:
0116 description:
0117 Target module reset bit in the RSTCTRL register if wired for the module.
0118 Note that the other reset bits should be mapped for the child device
0119 driver to use.
0120 maxItems: 1
0121
0122 reset-names:
0123 description:
0124 Target module reset names in the RSTCTRL register, typically named
0125 "rstctrl" if only one reset bit is wired for the module.
0126 items:
0127 - const: rstctrl
0128
0129 '#address-cells':
0130 enum: [ 1, 2 ]
0131
0132 '#size-cells':
0133 enum: [ 1, 2 ]
0134
0135 ranges: true
0136
0137 dma-ranges: true
0138
0139 ti,sysc-mask:
0140 description: Mask of supported register bits for the SYSCONFIG register
0141 $ref: /schemas/types.yaml#/definitions/uint32
0142
0143 ti,sysc-midle:
0144 description: List of hardware supported idle modes
0145 $ref: /schemas/types.yaml#/definitions/uint32-array
0146
0147 ti,sysc-sidle:
0148 description: List of hardware supported idle modes
0149 $ref: /schemas/types.yaml#/definitions/uint32-array
0150
0151 ti,syss-mask:
0152 description: Mask of supported register bits for the SYSSTATUS register
0153 $ref: /schemas/types.yaml#/definitions/uint32
0154
0155 ti,sysc-delay-us:
0156 description: Delay needed after OCP softreset before accessing SYCONFIG
0157 default: 0
0158 minimum: 0
0159 maximum: 2
0160
0161 ti,no-reset-on-init:
0162 description: Interconnect target module shall not be reset at init
0163 type: boolean
0164
0165 ti,no-idle-on-init:
0166 description: Interconnect target module shall not be idled at init
0167 type: boolean
0168
0169 ti,no-idle:
0170 description: Interconnect target module shall not be idled
0171 type: boolean
0172
0173 ti,hwmods:
0174 description: Interconnect module name to use with legacy hwmod data
0175 $ref: /schemas/types.yaml#/definitions/string
0176 deprecated: true
0177
0178 required:
0179 - compatible
0180 - '#address-cells'
0181 - '#size-cells'
0182 - ranges
0183
0184 additionalProperties:
0185 type: object
0186
0187 examples:
0188 - |
0189 #include <dt-bindings/bus/ti-sysc.h>
0190 #include <dt-bindings/clock/omap4.h>
0191
0192 target-module@2b000 {
0193 compatible = "ti,sysc-omap2", "ti,sysc";
0194 ti,hwmods = "usb_otg_hs";
0195 reg = <0x2b400 0x4>,
0196 <0x2b404 0x4>,
0197 <0x2b408 0x4>;
0198 reg-names = "rev", "sysc", "syss";
0199 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
0200 clock-names = "fck";
0201 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
0202 SYSC_OMAP2_SOFTRESET |
0203 SYSC_OMAP2_AUTOIDLE)>;
0204 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0205 <SYSC_IDLE_NO>,
0206 <SYSC_IDLE_SMART>;
0207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0208 <SYSC_IDLE_NO>,
0209 <SYSC_IDLE_SMART>,
0210 <SYSC_IDLE_SMART_WKUP>;
0211 ti,syss-mask = <1>;
0212 #address-cells = <1>;
0213 #size-cells = <1>;
0214 ranges = <0 0x2b000 0x1000>;
0215 };
